1 /** @file 2 SMRAM Save State Map Definitions. 3 4 SMRAM Save State Map definitions based on contents of the 5 Intel(R) 64 and IA-32 Architectures Software Developer's Manual 6 Volume 3C, Section 34.4 SMRAM 7 Volume 3C, Section 34.5 SMI Handler Execution Environment 8 Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs 9 10 and the AMD64 Architecture Programmer's Manual 11 Volume 2, Section 10.2 SMM Resources 12 13 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> 14 Copyright (c) 2015, Red Hat, Inc.<BR> 15 This program and the accompanying materials 16 are licensed and made available under the terms and conditions of the BSD License 17 which accompanies this distribution. The full text of the license may be found at 18 http://opensource.org/licenses/bsd-license.php 19 20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 21 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 22 23 **/ 24 25 #ifndef __QEMU_SMRAM_SAVE_STATE_MAP_H__ 26 #define __QEMU_SMRAM_SAVE_STATE_MAP_H__ 27 28 #pragma pack (1) 29 30 /// 31 /// 32-bit SMRAM Save State Map 32 /// 33 typedef struct { 34 UINT8 Reserved0[0x200]; // 7c00h 35 UINT8 Reserved1[0xf8]; // 7e00h 36 UINT32 SMBASE; // 7ef8h 37 UINT32 SMMRevId; // 7efch 38 UINT16 IORestart; // 7f00h 39 UINT16 AutoHALTRestart; // 7f02h 40 UINT8 Reserved2[0x9C]; // 7f08h 41 UINT32 IOMemAddr; // 7fa0h 42 UINT32 IOMisc; // 7fa4h 43 UINT32 _ES; // 7fa8h 44 UINT32 _CS; // 7fach 45 UINT32 _SS; // 7fb0h 46 UINT32 _DS; // 7fb4h 47 UINT32 _FS; // 7fb8h 48 UINT32 _GS; // 7fbch 49 UINT32 Reserved3; // 7fc0h 50 UINT32 _TR; // 7fc4h 51 UINT32 _DR7; // 7fc8h 52 UINT32 _DR6; // 7fcch 53 UINT32 _EAX; // 7fd0h 54 UINT32 _ECX; // 7fd4h 55 UINT32 _EDX; // 7fd8h 56 UINT32 _EBX; // 7fdch 57 UINT32 _ESP; // 7fe0h 58 UINT32 _EBP; // 7fe4h 59 UINT32 _ESI; // 7fe8h 60 UINT32 _EDI; // 7fech 61 UINT32 _EIP; // 7ff0h 62 UINT32 _EFLAGS; // 7ff4h 63 UINT32 _CR3; // 7ff8h 64 UINT32 _CR0; // 7ffch 65 } QEMU_SMRAM_SAVE_STATE_MAP32; 66 67 /// 68 /// 64-bit SMRAM Save State Map 69 /// 70 typedef struct { 71 UINT8 Reserved0[0x200]; // 7c00h 72 73 UINT16 _ES; // 7e00h 74 UINT16 _ESAccessRights; // 7e02h 75 UINT32 _ESLimit; // 7e04h 76 UINT64 _ESBase; // 7e08h 77 78 UINT16 _CS; // 7e10h 79 UINT16 _CSAccessRights; // 7e12h 80 UINT32 _CSLimit; // 7e14h 81 UINT64 _CSBase; // 7e18h 82 83 UINT16 _SS; // 7e20h 84 UINT16 _SSAccessRights; // 7e22h 85 UINT32 _SSLimit; // 7e24h 86 UINT64 _SSBase; // 7e28h 87 88 UINT16 _DS; // 7e30h 89 UINT16 _DSAccessRights; // 7e32h 90 UINT32 _DSLimit; // 7e34h 91 UINT64 _DSBase; // 7e38h 92 93 UINT16 _FS; // 7e40h 94 UINT16 _FSAccessRights; // 7e42h 95 UINT32 _FSLimit; // 7e44h 96 UINT64 _FSBase; // 7e48h 97 98 UINT16 _GS; // 7e50h 99 UINT16 _GSAccessRights; // 7e52h 100 UINT32 _GSLimit; // 7e54h 101 UINT64 _GSBase; // 7e58h 102 103 UINT32 _GDTRReserved1; // 7e60h 104 UINT16 _GDTRLimit; // 7e64h 105 UINT16 _GDTRReserved2; // 7e66h 106 UINT64 _GDTRBase; // 7e68h 107 108 UINT16 _LDTR; // 7e70h 109 UINT16 _LDTRAccessRights; // 7e72h 110 UINT32 _LDTRLimit; // 7e74h 111 UINT64 _LDTRBase; // 7e78h 112 113 UINT32 _IDTRReserved1; // 7e80h 114 UINT16 _IDTRLimit; // 7e84h 115 UINT16 _IDTRReserved2; // 7e86h 116 UINT64 _IDTRBase; // 7e88h 117 118 UINT16 _TR; // 7e90h 119 UINT16 _TRAccessRights; // 7e92h 120 UINT32 _TRLimit; // 7e94h 121 UINT64 _TRBase; // 7e98h 122 123 UINT64 IO_RIP; // 7ea0h 124 UINT64 IO_RCX; // 7ea8h 125 UINT64 IO_RSI; // 7eb0h 126 UINT64 IO_RDI; // 7eb8h 127 UINT32 IO_DWord; // 7ec0h 128 UINT8 Reserved1[0x04]; // 7ec4h 129 UINT8 IORestart; // 7ec8h 130 UINT8 AutoHALTRestart; // 7ec9h 131 UINT8 Reserved2[0x06]; // 7ecah 132 133 UINT64 IA32_EFER; // 7ed0h 134 UINT64 SVM_Guest; // 7ed8h 135 UINT64 SVM_GuestVMCB; // 7ee0h 136 UINT64 SVM_GuestVIntr; // 7ee8h 137 UINT8 Reserved3[0x0c]; // 7ef0h 138 139 UINT32 SMMRevId; // 7efch 140 UINT32 SMBASE; // 7f00h 141 142 UINT8 Reserved4[0x1c]; // 7f04h 143 UINT64 SVM_GuestPAT; // 7f20h 144 UINT64 SVM_HostIA32_EFER; // 7f28h 145 UINT64 SVM_HostCR4; // 7f30h 146 UINT64 SVM_HostCR3; // 7f38h 147 UINT64 SVM_HostCR0; // 7f40h 148 149 UINT64 _CR4; // 7f48h 150 UINT64 _CR3; // 7f50h 151 UINT64 _CR0; // 7f58h 152 UINT64 _DR7; // 7f60h 153 UINT64 _DR6; // 7f68h 154 UINT64 _RFLAGS; // 7f70h 155 UINT64 _RIP; // 7f78h 156 UINT64 _R15; // 7f80h 157 UINT64 _R14; // 7f88h 158 UINT64 _R13; // 7f90h 159 UINT64 _R12; // 7f98h 160 UINT64 _R11; // 7fa0h 161 UINT64 _R10; // 7fa8h 162 UINT64 _R9; // 7fb0h 163 UINT64 _R8; // 7fb8h 164 UINT64 _RDI; // 7fc0h 165 UINT64 _RSI; // 7fc8h 166 UINT64 _RBP; // 7fd0h 167 UINT64 _RSP; // 7fd8h 168 UINT64 _RBX; // 7fe0h 169 UINT64 _RDX; // 7fe8h 170 UINT64 _RCX; // 7ff0h 171 UINT64 _RAX; // 7ff8h 172 } QEMU_SMRAM_SAVE_STATE_MAP64; 173 174 /// 175 /// Union of 32-bit and 64-bit SMRAM Save State Maps 176 /// 177 typedef union { 178 QEMU_SMRAM_SAVE_STATE_MAP32 x86; 179 QEMU_SMRAM_SAVE_STATE_MAP64 x64; 180 } QEMU_SMRAM_SAVE_STATE_MAP; 181 182 #pragma pack () 183 184 #endif 185
