1 2 /*----------------------------------------------------------------------------- 3 ------------------------------------------------------------------------------- 4 5 6 Intel Silvermont Processor Power Management BIOS Reference Code 7 8 Copyright (c) 2006 - 2014, Intel Corporation 9 10 This program and the accompanying materials are licensed and made available under 11 the terms and conditions of the BSD License that accompanies this distribution. 12 The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php. 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 19 Filename: CPU0CST.ASL 20 21 Revision: Refer to Readme 22 23 Date: Refer to Readme 24 25 -------------------------------------------------------------------------------- 26 ------------------------------------------------------------------------------- 27 28 This Processor Power Management BIOS Source Code is furnished under license 29 and may only be used or copied in accordance with the terms of the license. 30 The information in this document is furnished for informational use only, is 31 subject to change without notice, and should not be construed as a commitment 32 by Intel Corporation. Intel Corporation assumes no responsibility or liability 33 for any errors or inaccuracies that may appear in this document or any 34 software that may be provided in association with this document. 35 36 Except as permitted by such license, no part of this document may be 37 reproduced, stored in a retrieval system, or transmitted in any form or by 38 any means without the express written consent of Intel Corporation. 39 40 WARNING: You are authorized and licensed to install and use this BIOS code 41 ONLY on an IST PC. This utility may damage any system that does not 42 meet these requirements. 43 44 An IST PC is a computer which 45 (1) Is capable of seamlessly and automatically transitioning among 46 multiple performance states (potentially operating at different 47 efficiency ratings) based upon power source changes, END user 48 preference, processor performance demand, and thermal conditions; and 49 (2) Includes an Intel Pentium II processors, Intel Pentium III 50 processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 51 Processor-M, Intel Pentium M Processor, or any other future Intel 52 processors that incorporates the capability to transition between 53 different performance states by altering some, or any combination of, 54 the following processor attributes: core voltage, core frequency, bus 55 frequency, number of processor cores available, or any other attribute 56 that changes the efficiency (instructions/unit time-power) at which the 57 processor operates. 58 59 ------------------------------------------------------------------------------- 60 ------------------------------------------------------------------------------- 61 62 NOTES: 63 (1) <TODO> - IF the trap range and port definitions do not match those 64 specified by this reference code, this file must be modified IAW the 65 individual implmentation. 66 67 -------------------------------------------------------------------------------- 68 ------------------------------------------------------------------------------*/ 69 70 71 DefinitionBlock ( 72 "CPU0CST.aml", 73 "SSDT", 74 1, 75 "PmRef", 76 "Cpu0Cst", 77 0x3001 78 ) 79 { 80 External(\_PR.CPU0, DeviceObj) 81 External(PWRS) 82 External(CFGD) 83 External(PDC0) 84 85 Scope(\_PR.CPU0) 86 { 87 OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG 88 Field (DEB0, ByteAcc,NoLock,Preserve) //DBG 89 { DBG8, 8,} //DBG 90 91 Method (_CST, 0) 92 { 93 Store(0x60,DBG8) //DBG 94 95 // IF CMP is supported, but independent C-States beyond C1 are 96 // not supported; return C1 Halt and rely on BIOS based software 97 // coordination 98 // 99 // CFGD[24] = CMP support 100 // PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems 101 // 102 // Note: SMI will be generated when both processor enter the 103 // Halt state. 104 // 105 If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10)))) 106 { 107 Store(0x61,DBG8) //DBG 108 Return(Package() { 109 1, 110 Package() 111 { // C1 halt, but with BIOS coordination 112 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, 113 1, 114 157, 115 1000 116 } 117 }) 118 } 119 120 // IF MWAIT extensions are supported, use them. 121 // 122 // IF C6 capable/enabled AND Battery 123 // Report MWAIT C1, C2, C6 w/ BM_STS avoidance 124 // ELSE IF C4 capable/enabled AND Battery 125 // Report MWAIT C1, C2, C4 w/ BM_STS avoidance 126 // ELSE IF C3 capable/enabled 127 // Report MWAIT C1, C2, C3 w/ BM_STS avoidance 128 // ELSE IF C2 capable/enabled 129 // Report MWAIT C1, C2 130 // ELSE 131 // Report MWAIT C1 132 // 133 // CFGD[21] = 1 - MWAIT extensions supported 134 // CFGD[13] = 1 - C7 Capable/Enabled 135 // CFGD[12] = 1 - C6S Capable/Enabled 136 // CFGD[11] = 1 - C6 Capable/Enabled 137 // CFGD[7] = 1 - C4 Capable/Enabled 138 // CFGD[5] = 1 - C3 Capable/Enabled 139 // PDCx[9] = 1 - OS supports MWAIT extensions 140 // PDCx[8] = 1 - OS supports MWAIT for C1 141 // (Inferred from PDCx[9] = 1.) 142 // PDCx[4] = 1 - OS supports independent C2/C3 in MP systems 143 // or 144 // NOT CMP (Inferred from previous check.) 145 // 146 If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200))) 147 { 148 // 149 // <TODO> The implementor may wish to only report C1-C2 150 // when on AC power. In this case, the IF clause below can 151 // be modified to something like: 152 // 153 // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))" 154 // 155 // Which uses the power state of the system (PWRS) to 156 // determine whether to allow deepers states. 157 // 158 // IF C7 supported AND on battery 159 // report MWAIT C1, C6, C7 160 // 161 // CFGD[13] = C7 Capable/Enabled 162 // CFGD[11] = C6 Capable/Enabled 163 // 164 If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000))) 165 { 166 Store(0x77,DBG8) //DBG 167 Return( Package() 168 { 169 3, 170 Package() 171 { // C1, MWAIT 172 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, 173 1, 174 1, 175 1000 176 }, 177 Package() 178 { 179 // C6, MWAIT Extension with Incremental L2 Shrink 180 // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)}, 181 // C6, MWAIT Extension with No L2 Shrink 182 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)}, 183 2, 184 500, 185 10 186 }, 187 Package() 188 { 189 // C7, MWAIT Extension with Full L2 Shrink 190 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)}, 191 3, 192 1500, //PnP setting, 1.5 ms for worst-case exit latency 193 10 194 } 195 }) 196 } 197 198 199 If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000)))) 200 { 201 Store(0x67,DBG8) //DBG 202 Return( Package() 203 { 204 3, 205 Package() 206 { // C1, MWAIT 207 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, 208 1, 209 1, 210 1000 211 }, 212 Package() 213 { 214 // C6, MWAIT Extension with Incremental L2 Shrink 215 // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)}, 216 // C6 = C6NS, MWAIT Extension with No L2 Shrink 217 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)}, 218 2, 219 500, 220 10 221 }, 222 Package() 223 { 224 225 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)}, 226 3, 227 1500, //PnP setting, 1.5 ms for worst-case exit latency 228 10 229 } 230 }) 231 } 232 233 If(And(CFGD,0x800)) // Setup Max C-State = C6 234 { 235 Store(0x76,DBG8) //DBG 236 Return( Package() 237 { 238 2, 239 Package() 240 { // C1, MWAIT 241 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, 242 1, 243 1, 244 1000 245 }, 246 Package() 247 { 248 // C6, MWAIT Extension with Incremental L2 Shrink 249 // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)}, 250 // C6, MWAIT Extension with No L2 Shrink 251 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)}, 252 2, 253 500, 254 10 255 } 256 }) 257 } 258 // 259 // IF no deeper C-States are supported; report MWAIT C1. 260 // 261 Store(0x71,DBG8) //DBG 262 Return(Package() 263 { 264 1, 265 Package() 266 { // C1, MWAIT 267 ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)}, 268 1, 269 1, 270 1000 271 } 272 }) 273 } 274 275 276 } 277 } 278 } 279 280 281
