1 /*----------------------------------------------------------------------------- 2 ------------------------------------------------------------------------------- 3 4 5 Intel Silvermont Processor Power Management BIOS Reference Code 6 7 Copyright (c) 2006 - 2014, Intel Corporation 8 9 This program and the accompanying materials are licensed and made available under 10 the terms and conditions of the BSD License that accompanies this distribution. 11 The full text of the license may be found at 12 http://opensource.org/licenses/bsd-license.php. 13 14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 16 17 18 Filename: CPU0TST.ASL 19 20 Revision: Refer to Readme 21 22 Date: Refer to Readme 23 24 -------------------------------------------------------------------------------- 25 ------------------------------------------------------------------------------- 26 27 This Processor Power Management BIOS Source Code is furnished under license 28 and may only be used or copied in accordance with the terms of the license. 29 The information in this document is furnished for informational use only, is 30 subject to change without notice, and should not be construed as a commitment 31 by Intel Corporation. Intel Corporation assumes no responsibility or liability 32 for any errors or inaccuracies that may appear in this document or any 33 software that may be provided in association with this document. 34 35 Except as permitted by such license, no part of this document may be 36 reproduced, stored in a retrieval system, or transmitted in any form or by 37 any means without the express written consent of Intel Corporation. 38 39 WARNING: You are authorized and licensed to install and use this BIOS code 40 ONLY on an IST PC. This utility may damage any system that does not 41 meet these requirements. 42 43 An IST PC is a computer which 44 (1) Is capable of seamlessly and automatically transitioning among 45 multiple performance states (potentially operating at different 46 efficiency ratings) based upon power source changes, end user 47 preference, processor performance demand, and thermal conditions; and 48 (2) Includes an Intel Pentium II processors, Intel Pentium III 49 processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 50 Processor-M, Intel Pentium M Processor, or any other future Intel 51 processors that incorporates the capability to transition between 52 different performance states by altering some, or any combination of, 53 the following processor attributes: core voltage, core frequency, bus 54 frequency, number of processor cores available, or any other attribute 55 that changes the efficiency (instructions/unit time-power) at which the 56 processor operates. 57 58 ------------------------------------------------------------------------------- 59 ------------------------------------------------------------------------------- 60 61 NOTES: 62 (1) <TODO> - IF the trap range and port definitions do not match those 63 specified by this reference code, this file must be modified IAW the 64 individual implmentation. 65 66 -------------------------------------------------------------------------------- 67 ------------------------------------------------------------------------------*/ 68 69 DefinitionBlock( 70 "CPU0TST.aml", 71 "SSDT", 72 0x01, 73 "PmRef", 74 "Cpu0Tst", 75 0x3000 76 ) 77 { 78 External(\_PR.CPU0, DeviceObj) 79 External(PDC0) 80 External(CFGD) 81 External(_PSS) 82 83 Scope(\_PR.CPU0) 84 { 85 Name(_TPC, 0) // All T-States are available 86 87 // 88 // T-State Control/Status interface 89 // 90 Method(_PTC, 0) 91 { 92 // 93 // IF OSPM is capable of direct access to MSR 94 // Report MSR interface 95 // ELSE 96 // Report I/O interface 97 // 98 // PDCx[2] = OSPM is capable of direct access to On 99 // Demand throttling MSR 100 // 101 If(And(PDC0, 0x0004)) { 102 Return(Package() { 103 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, 104 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} 105 }) 106 } 107 108 } 109 110 // _TSS package for I/O port based T-State control 111 // "Power" fields are replaced with real values by the first 112 // call of _TSS method. 113 // 114 Name(TSSI, Package() { 115 Package(){100, 1000, 0, 0x00, 0}, 116 Package(){ 88, 875, 0, 0x0F, 0}, 117 Package(){ 75, 750, 0, 0x0E, 0}, 118 Package(){ 63, 625, 0, 0x0D, 0}, 119 Package(){ 50, 500, 0, 0x0C, 0}, 120 Package(){ 38, 375, 0, 0x0B, 0}, 121 Package(){ 25, 250, 0, 0x0A, 0}, 122 Package(){ 13, 125, 0, 0x09, 0} 123 }) 124 125 // _TSS package for MSR based T-State control 126 // "Power" fields are replaced with real values by the first 127 // call of _TSS method. 128 // 129 Name(TSSM, Package() { 130 Package(){100, 1000, 0, 0x00, 0}, 131 Package(){ 88, 875, 0, 0x1E, 0}, 132 Package(){ 75, 750, 0, 0x1C, 0}, 133 Package(){ 63, 625, 0, 0x1A, 0}, 134 Package(){ 50, 500, 0, 0x18, 0}, 135 Package(){ 38, 375, 0, 0x16, 0}, 136 Package(){ 25, 250, 0, 0x14, 0}, 137 Package(){ 13, 125, 0, 0x12, 0} 138 }) 139 140 Name(TSSF, 0) // Flag for TSSI/TSSM initialization 141 142 Method(_TSS, 0) 143 { 144 // Update "Power" fields of TSSI/TSSM with the LFM 145 // power data IF _PSS is available 146 // 147 IF (LAnd(LNot(TSSF),CondRefOf(_PSS))) 148 { 149 Store(_PSS, Local0) 150 Store(SizeOf(Local0), Local1) // _PSS size 151 Decrement(Local1) // Index of LFM 152 Store(DerefOf(Index(DerefOf(Index(Local0,Local1)),1)), Local2) // LFM Power 153 154 Store(0, Local3) 155 While(LLess(Local3, SizeOf(TSSI))) 156 { 157 Store(Divide(Multiply(Local2, Subtract(8, Local3)), 8), 158 Local4) // Power for this TSSI/TSSM entry 159 Store(Local4,Index(DerefOf(Index(TSSI,Local3)),1)) 160 Store(Local4,Index(DerefOf(Index(TSSM,Local3)),1)) 161 Increment(Local3) 162 } 163 Store(Ones, TSSF) // TSSI/TSSM are updated 164 } 165 // 166 // IF OSPM is capable of direct access to MSR 167 // Report TSSM 168 // ELSE 169 // Report TSSI 170 // 171 If(And(PDC0, 0x0004)) 172 { 173 Return(TSSM) 174 } 175 Return(TSSI) 176 } 177 178 Method(_TDL, 0) 179 { 180 Store ("Cpu0: _TDL Called", Debug) 181 Name ( LFMI, 0) 182 Store (SizeOf(TSSM), LFMI) 183 Decrement(LFMI) // Index of LFM entry in TSSM 184 Return(LFMI) 185 } 186 187 // 188 // T-State Dependency 189 // 190 Method(_TSD, 0) 191 { 192 // 193 // IF four cores are supported/enabled && !(direct access to MSR) 194 // Report 4 processors and SW_ANY as the coordination type 195 // ELSE IF two cores are supported/enabled && !(direct access to MSR) 196 // Report 2 processors and SW_ANY as the coordination type 197 // ELSE 198 // Report 1 processor and SW_ALL as the coordination type 199 // 200 // CFGD[23] = Four cores enabled 201 // CFGD[24] = Two or more cores enabled 202 // PDCx[2] = OSPM is capable of direct access to On 203 // Demand throttling MSR 204 // 205 If(LAnd(And(CFGD,0x0800000),LNot(And(PDC0,4)))) 206 { 207 Return(Package(){ // SW_ANY 208 Package(){ 209 5, // # entries. 210 0, // Revision. 211 0, // Domain #. 212 0xFD, // Coord Type- SW_ANY 213 4 // # processors. 214 } 215 }) 216 } 217 If(LAnd(And(CFGD,0x1000000),LNot(And(PDC0,4)))) 218 { 219 Return(Package(){ // SW_ANY 220 Package(){ 221 5, // # entries. 222 0, // Revision. 223 0, // Domain #. 224 0xFD, // Coord Type- SW_ANY 225 2 // # processors. 226 } 227 }) 228 } 229 Return(Package(){ // SW_ALL 230 Package(){ 231 5, // # entries. 232 0, // Revision. 233 0, // Domain #. 234 0xFC, // Coord Type- SW_ALL 235 1 // # processors. 236 } 237 }) 238 } 239 } 240 } // End of Definition Block 241 242
