1 2 /*++ 3 4 Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved 5 6 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 8 The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php. 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 15 16 Module Name: 17 18 vlvAccess.h 19 20 Abstract: 21 22 Macros to simplify and abstract the interface to PCI configuration. 23 24 --*/ 25 26 #ifndef _VLVACCESS_H_INCLUDED_ 27 #define _VLVACCESS_H_INCLUDED_ 28 29 #include "Valleyview.h" 30 #include "VlvCommonDefinitions.h" 31 #include <Library/IoLib.h> 32 33 // 34 // Memory Mapped IO access macros used by MSG BUS LIBRARY 35 // 36 #define MmioAddress( BaseAddr, Register ) \ 37 ( (UINTN)BaseAddr + \ 38 (UINTN)(Register) \ 39 ) 40 41 42 // 43 // UINT32 44 // 45 46 #define Mmio32Ptr( BaseAddr, Register ) \ 47 ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) 48 49 #define Mmio32( BaseAddr, Register ) \ 50 *Mmio32Ptr( BaseAddr, Register ) 51 52 #define Mmio32Or( BaseAddr, Register, OrData ) \ 53 Mmio32( BaseAddr, Register ) = \ 54 (UINT32) ( \ 55 Mmio32( BaseAddr, Register ) | \ 56 (UINT32)(OrData) \ 57 ) 58 59 #define Mmio32And( BaseAddr, Register, AndData ) \ 60 Mmio32( BaseAddr, Register ) = \ 61 (UINT32) ( \ 62 Mmio32( BaseAddr, Register ) & \ 63 (UINT32)(AndData) \ 64 ) 65 66 #define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \ 67 Mmio32( BaseAddr, Register ) = \ 68 (UINT32) ( \ 69 ( Mmio32( BaseAddr, Register ) & \ 70 (UINT32)(AndData) \ 71 ) | \ 72 (UINT32)(OrData) \ 73 ) 74 75 // 76 // UINT16 77 // 78 79 #define Mmio16Ptr( BaseAddr, Register ) \ 80 ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) ) 81 82 #define Mmio16( BaseAddr, Register ) \ 83 *Mmio16Ptr( BaseAddr, Register ) 84 85 #define Mmio16Or( BaseAddr, Register, OrData ) \ 86 Mmio16( BaseAddr, Register ) = \ 87 (UINT16) ( \ 88 Mmio16( BaseAddr, Register ) | \ 89 (UINT16)(OrData) \ 90 ) 91 92 #define Mmio16And( BaseAddr, Register, AndData ) \ 93 Mmio16( BaseAddr, Register ) = \ 94 (UINT16) ( \ 95 Mmio16( BaseAddr, Register ) & \ 96 (UINT16)(AndData) \ 97 ) 98 99 #define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \ 100 Mmio16( BaseAddr, Register ) = \ 101 (UINT16) ( \ 102 ( Mmio16( BaseAddr, Register ) & \ 103 (UINT16)(AndData) \ 104 ) | \ 105 (UINT16)(OrData) \ 106 ) 107 108 // 109 // UINT8 110 // 111 112 #define Mmio8Ptr( BaseAddr, Register ) \ 113 ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) ) 114 115 #define Mmio8( BaseAddr, Register ) \ 116 *Mmio8Ptr( BaseAddr, Register ) 117 118 #define Mmio8Or( BaseAddr, Register, OrData ) \ 119 Mmio8( BaseAddr, Register ) = \ 120 (UINT8) ( \ 121 Mmio8( BaseAddr, Register ) | \ 122 (UINT8)(OrData) \ 123 ) 124 125 #define Mmio8And( BaseAddr, Register, AndData ) \ 126 Mmio8( BaseAddr, Register ) = \ 127 (UINT8) ( \ 128 Mmio8( BaseAddr, Register ) & \ 129 (UINT8)(AndData) \ 130 ) 131 132 #define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \ 133 Mmio8( BaseAddr, Register ) = \ 134 (UINT8) ( \ 135 ( Mmio8( BaseAddr, Register ) & \ 136 (UINT8)(AndData) \ 137 ) | \ 138 (UINT8)(OrData) \ 139 ) 140 141 // 142 // MSG BUS API 143 // 144 145 #define MSG_BUS_ENABLED 0x000000F0 146 #define MSGBUS_MASKHI 0xFFFFFF00 147 #define MSGBUS_MASKLO 0x000000FF 148 149 #define MESSAGE_BYTE_EN BIT4 150 #define MESSAGE_WORD_EN BIT4 | BIT5 151 #define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7 152 153 #define SIDEBAND_OPCODE 0x78 154 #define MEMREAD_OPCODE 0x00000000 155 #define MEMWRITE_OPCODE 0x01000000 156 157 158 159 /***************************/ 160 // 161 // Memory mapped PCI IO 162 // 163 164 #define PciCfgPtr(Bus, Device, Function, Register )\ 165 (UINTN)(Bus << 20) + \ 166 (UINTN)(Device << 15) + \ 167 (UINTN)(Function << 12) + \ 168 (UINTN)(Register) 169 170 #define PciCfg32Read_CF8CFC(B,D,F,R) \ 171 (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC)) 172 173 #define PciCfg32Write_CF8CFC(B,D,F,R,Data) \ 174 (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data)) 175 176 #define PciCfg32Or_CF8CFC(B,D,F,R,O) \ 177 PciCfg32Write_CF8CFC(B,D,F,R, \ 178 (PciCfg32Read_CF8CFC(B,D,F,R) | (O))) 179 180 #define PciCfg32And_CF8CFC(B,D,F,R,A) \ 181 PciCfg32Write_CF8CFC(B,D,F,R, \ 182 (PciCfg32Read_CF8CFC(B,D,F,R) & (A))) 183 184 #define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \ 185 PciCfg32Write_CF8CFC(B,D,F,R, \ 186 (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O)) 187 188 // 189 // Device 0, Function 0 190 // 191 #define McD0PciCfg64(Register) MmPci64 (0, MC_BUS, 0, 0, Register) 192 #define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 0, 0, Register, OrData) 193 #define McD0PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 0, 0, Register, AndData) 194 #define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 195 196 #define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register) 197 #define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData) 198 #define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData) 199 #define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 200 201 #define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register) 202 #define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData) 203 #define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData) 204 #define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 205 206 #define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register) 207 #define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData) 208 #define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData) 209 #define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) 210 211 212 // 213 // Device 2, Function 0 214 // 215 #define McD2PciCfg64(Register) MmPci64 (0, MC_BUS, 2, 0, Register) 216 #define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 2, 0, Register, OrData) 217 #define McD2PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 2, 0, Register, AndData) 218 #define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData) 219 220 #define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register) 221 #define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData) 222 #define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData) 223 #define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData) 224 225 #define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register) 226 #define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData) 227 #define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData) 228 #define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData) 229 230 #define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register) 231 #define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData) 232 #define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData) 233 234 // 235 // IO 236 // 237 238 #ifndef IoIn8 239 240 #define IoIn8(Port) \ 241 IoRead8(Port) 242 243 #define IoIn16(Port) \ 244 IoRead16(Port) 245 246 #define IoIn32(Port) \ 247 IoRead32(Port) 248 249 #define IoOut8(Port, Data) \ 250 IoWrite8(Port, Data) 251 252 #define IoOut16(Port, Data) \ 253 IoWrite16(Port, Data) 254 255 #define IoOut32(Port, Data) \ 256 IoWrite32(Port, Data) 257 258 #endif 259 260 #endif 261
