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      1 /**
      2 
      3 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
      4 
      5   This program and the accompanying materials are licensed and made available under
      6   the terms and conditions of the BSD License that accompanies this distribution.
      7   The full text of the license may be found at
      8   http://opensource.org/licenses/bsd-license.php.
      9 
     10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     12 
     13 
     14 
     15   @file
     16   PchRegsRcrb.h
     17 
     18   @brief
     19   Register names for VLV Chipset Configuration Registers
     20 
     21   Conventions:
     22 
     23   - Prefixes:
     24     Definitions beginning with "R_" are registers
     25     Definitions beginning with "B_" are bits within registers
     26     Definitions beginning with "V_" are meaningful values of bits within the registers
     27     Definitions beginning with "S_" are register sizes
     28     Definitions beginning with "N_" are the bit position
     29   - In general, PCH registers are denoted by "_PCH_" in register names
     30   - Registers / bits that are different between PCH generations are denoted by
     31     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
     32   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
     33     at the end of the register/bit names
     34   - Registers / bits of new devices introduced in a PCH generation will be just named
     35     as "_PCH_" without <generation_name> inserted.
     36 
     37 **/
     38 #ifndef _PCH_REGS_RCRB_H_
     39 #define _PCH_REGS_RCRB_H_
     40 
     41 ///
     42 /// Chipset Configuration Registers (Memory space)
     43 /// RCBA
     44 ///
     45 #define R_PCH_RCRB_GCS                    0x00  // General Control and Status
     46 #define B_PCH_RCRB_GCS_BBSIZE             (BIT30 | BIT29) // Boot Block Size
     47 #define B_PCH_RCRB_GCS_BBS                (BIT11 | BIT10) // Boot BIOS Straps
     48 #define V_PCH_RCRB_GCS_BBS_SPI            (3 << 10) // Boot BIOS strapped to SPI
     49 #define V_PCH_RCRB_GCS_BBS_LPC            (0 << 10) // Boot BIOS strapped to LPC
     50 #define B_PCH_RCRB_GCS_TS                 BIT1 // Top Swap
     51 #define B_PCH_RCRB_GCS_BILD               BIT0 // BIOS Interface Lock-Down
     52 
     53 
     54 #endif
     55