1 /*++ 2 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> 4 5 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 9 The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php. 13 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 19 21 23 24 Module Name: 25 26 CpuIA32.h 27 28 Abstract: 29 30 --*/ 31 32 #ifndef _CPU_IA32_H 33 #define _CPU_IA32_H 34 35 typedef struct { 36 UINT32 RegEax; 37 UINT32 RegEbx; 38 UINT32 RegEcx; 39 UINT32 RegEdx; 40 } EFI_CPUID_REGISTER; 41 42 typedef struct { 43 UINT32 HeaderVersion; 44 UINT32 UpdateRevision; 45 UINT32 Date; 46 UINT32 ProcessorId; 47 UINT32 Checksum; 48 UINT32 LoaderRevision; 49 UINT32 ProcessorFlags; 50 UINT32 DataSize; 51 UINT32 TotalSize; 52 UINT8 Reserved[12]; 53 } EFI_CPU_MICROCODE_HEADER; 54 55 typedef struct { 56 UINT32 ExtendedSignatureCount; 57 UINT32 ExtendedTableChecksum; 58 UINT8 Reserved[12]; 59 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER; 60 61 typedef struct { 62 UINT32 ProcessorSignature; 63 UINT32 ProcessorFlag; 64 UINT32 ProcessorChecksum; 65 } EFI_CPU_MICROCODE_EXTENDED_TABLE; 66 67 typedef struct { 68 UINT32 Stepping : 4; 69 UINT32 Model : 4; 70 UINT32 Family : 4; 71 UINT32 Type : 2; 72 UINT32 Reserved1 : 2; 73 UINT32 ExtendedModel : 4; 74 UINT32 ExtendedFamily : 8; 75 UINT32 Reserved2 : 4; 76 } EFI_CPU_VERSION; 77 78 #define EFI_CPUID_SIGNATURE 0x0 79 #define EFI_CPUID_VERSION_INFO 0x1 80 #define EFI_CPUID_CACHE_INFO 0x2 81 #define EFI_CPUID_SERIAL_NUMBER 0x3 82 #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000 83 #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001 84 #define EFI_CPUID_BRAND_STRING1 0x80000002 85 #define EFI_CPUID_BRAND_STRING2 0x80000003 86 #define EFI_CPUID_BRAND_STRING3 0x80000004 87 88 #define EFI_MSR_IA32_PLATFORM_ID 0x17 89 #define EFI_MSR_IA32_APIC_BASE 0x1B 90 #define EFI_MSR_EBC_HARD_POWERON 0x2A 91 #define EFI_MSR_EBC_SOFT_POWERON 0x2B 92 #define BINIT_DRIVER_DISABLE 0x40 93 #define INTERNAL_MCERR_DISABLE 0x20 94 #define INITIATOR_MCERR_DISABLE 0x10 95 #define EFI_MSR_EBC_FREQUENCY_ID 0x2C 96 #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79 97 #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B 98 #define EFI_MSR_PSB_CLOCK_STATUS 0xCD 99 #define EFI_APIC_GLOBAL_ENABLE 0x800 100 #define EFI_MSR_IA32_MISC_ENABLE 0x1A0 101 #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000 102 #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008 103 #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004 104 #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002 105 #define FAST_STRING_ENABLE_BIT 0x00000001 106 107 #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200 108 #define EFI_CACHE_VARIABLE_MTRR_END 0x20F 109 #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF 110 #define EFI_CACHE_MTRR_VALID 0x800 111 #define EFI_CACHE_FIXED_MTRR_VALID 0x400 112 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000 113 #define EFI_MSR_VALID_MASK 0xFFFFFFFFF 114 #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000 115 #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF 116 117 #define EFI_IA32_MTRR_FIX64K_00000 0x250 118 #define EFI_IA32_MTRR_FIX16K_80000 0x258 119 #define EFI_IA32_MTRR_FIX16K_A0000 0x259 120 #define EFI_IA32_MTRR_FIX4K_C0000 0x268 121 #define EFI_IA32_MTRR_FIX4K_C8000 0x269 122 #define EFI_IA32_MTRR_FIX4K_D0000 0x26A 123 #define EFI_IA32_MTRR_FIX4K_D8000 0x26B 124 #define EFI_IA32_MTRR_FIX4K_E0000 0x26C 125 #define EFI_IA32_MTRR_FIX4K_E8000 0x26D 126 #define EFI_IA32_MTRR_FIX4K_F0000 0x26E 127 #define EFI_IA32_MTRR_FIX4K_F8000 0x26F 128 129 #define EFI_IA32_MCG_CAP 0x179 130 #define EFI_IA32_MCG_CTL 0x17B 131 #define EFI_IA32_MC0_CTL 0x400 132 #define EFI_IA32_MC0_STATUS 0x401 133 134 #define EFI_IA32_PERF_STATUS 0x198 135 #define EFI_IA32_PERF_CTL 0x199 136 137 #define EFI_CACHE_UNCACHEABLE 0 138 #define EFI_CACHE_WRITECOMBINING 1 139 #define EFI_CACHE_WRITETHROUGH 4 140 #define EFI_CACHE_WRITEPROTECTED 5 141 #define EFI_CACHE_WRITEBACK 6 142 143 // 144 // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number 145 // 146 #define EfiMakeCpuVersion(f, m, s) \ 147 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s))) 148 149 /** 150 Halt the Cpu 151 152 @param[in] None 153 154 @retval None 155 156 **/ 157 VOID 158 EFIAPI 159 EfiHalt ( 160 VOID 161 ); 162 163 /** 164 Write back and invalidate the Cpu cache 165 166 @param[in] None 167 168 @retval None 169 170 **/ 171 VOID 172 EFIAPI 173 EfiWbinvd ( 174 VOID 175 ); 176 177 /** 178 Invalidate the Cpu cache 179 180 @param[in] None 181 182 @retval None 183 184 **/ 185 VOID 186 EFIAPI 187 EfiInvd ( 188 VOID 189 ); 190 191 /** 192 Get the Cpu info by excute the CPUID instruction 193 194 @param[in] RegisterInEax The input value to put into register EAX 195 @param[in] Regs The Output value 196 197 @retval None 198 199 **/ 200 VOID 201 EFIAPI 202 EfiCpuid ( 203 IN UINT32 RegisterInEax, 204 OUT EFI_CPUID_REGISTER *Regs 205 ); 206 207 /** 208 When RegisterInEax != 4, the functionality is the same as EfiCpuid. 209 When RegisterInEax == 4, the function return the deterministic cache 210 parameters by excuting the CPUID instruction. 211 212 @param[in] RegisterInEax The input value to put into register EAX. 213 @param[in] CacheLevel The deterministic cache level. 214 @param[in] Regs The Output value. 215 216 @retval None 217 218 **/ 219 VOID 220 EFIAPI 221 EfiCpuidExt ( 222 IN UINT32 RegisterInEax, 223 IN UINT32 CacheLevel, 224 OUT EFI_CPUID_REGISTER *Regs 225 ); 226 227 /** 228 Read Cpu MSR 229 230 @param[in] Index The index value to select the register 231 232 @retval Return the read data 233 234 **/ 235 UINT64 236 EFIAPI 237 EfiReadMsr ( 238 IN UINT32 Index 239 ); 240 241 /** 242 Write Cpu MSR 243 244 @param[in] Index The index value to select the register 245 @param[in] Value The value to write to the selected register 246 247 @retval None 248 249 **/ 250 VOID 251 EFIAPI 252 EfiWriteMsr ( 253 IN UINT32 Index, 254 IN UINT64 Value 255 ); 256 257 /** 258 Read Time stamp 259 260 @param[in] None 261 262 @retval Return the read data 263 264 **/ 265 UINT64 266 EFIAPI 267 EfiReadTsc ( 268 VOID 269 ); 270 271 /** 272 Writing back and invalidate the cache,then diable it 273 274 @param[in] None 275 276 @retval None 277 278 **/ 279 VOID 280 EFIAPI 281 EfiDisableCache ( 282 VOID 283 ); 284 285 /** 286 Invalidate the cache,then Enable it 287 288 @param[in] None 289 290 @retval None 291 292 **/ 293 VOID 294 EFIAPI 295 EfiEnableCache ( 296 VOID 297 ); 298 299 /** 300 Get Eflags 301 302 @param[in] None 303 304 @retval Return the Eflags value 305 306 **/ 307 UINT32 308 EFIAPI 309 EfiGetEflags ( 310 VOID 311 ); 312 313 /** 314 Disable Interrupts 315 316 @param[in] None 317 318 @retval None 319 320 **/ 321 VOID 322 EFIAPI 323 EfiDisableInterrupts ( 324 VOID 325 ); 326 327 /** 328 Enable Interrupts 329 330 @param[in] None 331 332 @retval None 333 334 **/ 335 VOID 336 EFIAPI 337 EfiEnableInterrupts ( 338 VOID 339 ); 340 341 /** 342 Extract CPU detail version infomation 343 344 @param[in] FamilyId FamilyId, including ExtendedFamilyId 345 @param[in] Model Model, including ExtendedModel 346 @param[in] SteppingId SteppingId 347 @param[in] Processor Processor 348 349 **/ 350 VOID 351 EFIAPI 352 EfiCpuVersion ( 353 IN UINT16 *FamilyId, OPTIONAL 354 IN UINT8 *Model, OPTIONAL 355 IN UINT8 *SteppingId, OPTIONAL 356 IN UINT8 *Processor OPTIONAL 357 ); 358 359 #endif 360
