1 /* 2 3 Copyright (c) 2009, 2010, 2011, 2013 STMicroelectronics 4 Written by Christophe Lyon 5 6 Permission is hereby granted, free of charge, to any person obtaining a copy 7 of this software and associated documentation files (the "Software"), to deal 8 in the Software without restriction, including without limitation the rights 9 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 copies of the Software, and to permit persons to whom the Software is 11 furnished to do so, subject to the following conditions: 12 13 The above copyright notice and this permission notice shall be included in 14 all copies or substantial portions of the Software. 15 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 THE SOFTWARE. 23 24 */ 25 26 #if defined(__arm__) || defined(__aarch64__) 27 #include <arm_neon.h> 28 #else 29 #include "stm-arm-neon.h" 30 #endif 31 32 #include "stm-arm-neon-ref.h" 33 34 #ifndef INSN_NAME 35 #define INSN_NAME vmul 36 #define TEST_MSG "VMUL" 37 #endif 38 39 40 #define FNNAME1(NAME) void exec_ ## NAME (void) 41 #define FNNAME(NAME) FNNAME1(NAME) 42 43 FNNAME (INSN_NAME) 44 { 45 #define DECL_VMUL(T, W, N) \ 46 DECL_VARIABLE(vector1, T, W, N); \ 47 DECL_VARIABLE(vector2, T, W, N); \ 48 DECL_VARIABLE(vector_res, T, W, N) 49 50 /* vector_res = OP(vector1, vector2), then store the result. */ 51 #define TEST_VMUL1(INSN, Q, T1, T2, W, N) \ 52 VECT_VAR(vector_res, T1, W, N) = \ 53 INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \ 54 VECT_VAR(vector2, T1, W, N)); \ 55 vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ 56 VECT_VAR(vector_res, T1, W, N)) 57 58 #define TEST_VMUL(INSN, Q, T1, T2, W, N) \ 59 TEST_VMUL1(INSN, Q, T1, T2, W, N) 60 61 /* With ARM RVCT, we need to declare variables before any executable 62 statement */ 63 DECL_VMUL(int, 8, 8); 64 DECL_VMUL(int, 16, 4); 65 DECL_VMUL(int, 32, 2); 66 DECL_VMUL(uint, 8, 8); 67 DECL_VMUL(uint, 16, 4); 68 DECL_VMUL(uint, 32, 2); 69 DECL_VMUL(poly, 8, 8); 70 DECL_VMUL(float, 32, 2); 71 DECL_VMUL(int, 8, 16); 72 DECL_VMUL(int, 16, 8); 73 DECL_VMUL(int, 32, 4); 74 DECL_VMUL(uint, 8, 16); 75 DECL_VMUL(uint, 16, 8); 76 DECL_VMUL(uint, 32, 4); 77 DECL_VMUL(poly, 8, 16); 78 DECL_VMUL(float, 32, 4); 79 80 clean_results (); 81 82 VLOAD(vector1, buffer, , int, s, 8, 8); 83 VLOAD(vector1, buffer, , int, s, 16, 4); 84 VLOAD(vector1, buffer, , int, s, 32, 2); 85 VLOAD(vector1, buffer, , uint, u, 8, 8); 86 VLOAD(vector1, buffer, , uint, u, 16, 4); 87 VLOAD(vector1, buffer, , uint, u, 32, 2); 88 VLOAD(vector1, buffer, , poly, p, 8, 8); 89 VLOAD(vector1, buffer, , float, f, 32, 2); 90 VLOAD(vector1, buffer, q, int, s, 8, 16); 91 VLOAD(vector1, buffer, q, int, s, 16, 8); 92 VLOAD(vector1, buffer, q, int, s, 32, 4); 93 VLOAD(vector1, buffer, q, uint, u, 8, 16); 94 VLOAD(vector1, buffer, q, uint, u, 16, 8); 95 VLOAD(vector1, buffer, q, uint, u, 32, 4); 96 VLOAD(vector1, buffer, q, poly, p, 8, 16); 97 VLOAD(vector1, buffer, q, float, f, 32, 4); 98 99 VDUP(vector2, , int, s, 8, 8, 0x11); 100 VDUP(vector2, , int, s, 16, 4, 0x22); 101 VDUP(vector2, , int, s, 32, 2, 0x33); 102 VDUP(vector2, , uint, u, 8, 8, 0x44); 103 VDUP(vector2, , uint, u, 16, 4, 0x55); 104 VDUP(vector2, , uint, u, 32, 2, 0x66); 105 VDUP(vector2, , poly, p, 8, 8, 0x44); 106 VDUP(vector2, , float, f, 32, 2, 33.3f); 107 VDUP(vector2, q, int, s, 8, 16, 0x77); 108 VDUP(vector2, q, int, s, 16, 8, 0x88); 109 VDUP(vector2, q, int, s, 32, 4, 0x99); 110 VDUP(vector2, q, uint, u, 8, 16, 0xAA); 111 VDUP(vector2, q, uint, u, 16, 8, 0xBB); 112 VDUP(vector2, q, uint, u, 32, 4, 0xCC); 113 VDUP(vector2, q, poly, p, 8, 16, 0xAA); 114 VDUP(vector2, q, float, f, 32, 4, 99.6f); 115 116 TEST_VMUL(INSN_NAME, , int, s, 8, 8); 117 TEST_VMUL(INSN_NAME, , int, s, 16, 4); 118 TEST_VMUL(INSN_NAME, , int, s, 32, 2); 119 TEST_VMUL(INSN_NAME, , uint, u, 8, 8); 120 TEST_VMUL(INSN_NAME, , uint, u, 16, 4); 121 TEST_VMUL(INSN_NAME, , uint, u, 32, 2); 122 TEST_VMUL(INSN_NAME, , poly, p, 8, 8); 123 TEST_VMUL(INSN_NAME, , float, f, 32, 2); 124 TEST_VMUL(INSN_NAME, q, int, s, 8, 16); 125 TEST_VMUL(INSN_NAME, q, int, s, 16, 8); 126 TEST_VMUL(INSN_NAME, q, int, s, 32, 4); 127 TEST_VMUL(INSN_NAME, q, uint, u, 8, 16); 128 TEST_VMUL(INSN_NAME, q, uint, u, 16, 8); 129 TEST_VMUL(INSN_NAME, q, uint, u, 32, 4); 130 TEST_VMUL(INSN_NAME, q, poly, p, 8, 16); 131 TEST_VMUL(INSN_NAME, q, float, f, 32, 4); 132 133 dump_results_hex (TEST_MSG); 134 } 135
