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      1 /*
      2 
      3 Copyright (c) 2009, 2010, 2011, 2013 STMicroelectronics
      4 Written by Christophe Lyon
      5 
      6 Permission is hereby granted, free of charge, to any person obtaining a copy
      7 of this software and associated documentation files (the "Software"), to deal
      8 in the Software without restriction, including without limitation the rights
      9 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 copies of the Software, and to permit persons to whom the Software is
     11 furnished to do so, subject to the following conditions:
     12 
     13 The above copyright notice and this permission notice shall be included in
     14 all copies or substantial portions of the Software.
     15 
     16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
     19 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 THE SOFTWARE.
     23 
     24 */
     25 
     26 #if defined(__arm__) || defined(__aarch64__)
     27 #include <arm_neon.h>
     28 #else
     29 #include "stm-arm-neon.h"
     30 #endif
     31 
     32 #include "stm-arm-neon-ref.h"
     33 
     34 #ifndef INSN_NAME
     35 #define INSN_NAME vsli
     36 #define TEST_MSG "VSLI_N"
     37 #endif
     38 
     39 #define FNNAME1(NAME) void exec_ ## NAME ##_n (void)
     40 #define FNNAME(NAME) FNNAME1(NAME)
     41 
     42 FNNAME (INSN_NAME)
     43 {
     44   /* vector_res = vsxi_n(vector, vector2, val),
     45      then store the result.  */
     46 #define TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V)				\
     47   VECT_VAR(vector_res, T1, W, N) =					\
     48     INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N),			\
     49 			VECT_VAR(vector2, T1, W, N),			\
     50 			V);						\
     51   vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
     52 
     53 #define TEST_VSXI_N(INSN, Q, T1, T2, W, N, V)	\
     54   TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V)
     55 
     56   /* With ARM RVCT, we need to declare variables before any executable
     57      statement */
     58   DECL_VARIABLE_ALL_VARIANTS(vector);
     59   DECL_VARIABLE_ALL_VARIANTS(vector2);
     60   DECL_VARIABLE_ALL_VARIANTS(vector_res);
     61 
     62   clean_results ();
     63 
     64   /* Initialize input "vector" from "buffer"  */
     65   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
     66 
     67   /* Fill input vector2 with arbitrary values */
     68   VDUP(vector2, , int, s, 8, 8, 2);
     69   VDUP(vector2, , int, s, 16, 4, -4);
     70   VDUP(vector2, , int, s, 32, 2, 3);
     71   VDUP(vector2, , int, s, 64, 1, 100);
     72   VDUP(vector2, , uint, u, 8, 8, 20);
     73   VDUP(vector2, , uint, u, 16, 4, 30);
     74   VDUP(vector2, , uint, u, 32, 2, 40);
     75   VDUP(vector2, , uint, u, 64, 1, 2);
     76   VDUP(vector2, , poly, p, 8, 8, 20);
     77   VDUP(vector2, , poly, p, 16, 4, 30);
     78   VDUP(vector2, q, int, s, 8, 16, -10);
     79   VDUP(vector2, q, int, s, 16, 8, -20);
     80   VDUP(vector2, q, int, s, 32, 4, -30);
     81   VDUP(vector2, q, int, s, 64, 2, 24);
     82   VDUP(vector2, q, uint, u, 8, 16, 12);
     83   VDUP(vector2, q, uint, u, 16, 8, 3);
     84   VDUP(vector2, q, uint, u, 32, 4, 55);
     85   VDUP(vector2, q, uint, u, 64, 2, 3);
     86   VDUP(vector2, q, poly, p, 8, 16, 12);
     87   VDUP(vector2, q, poly, p, 16, 8, 3);
     88 
     89   /* Choose shift amount arbitrarily */
     90   TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 4);
     91   TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 3);
     92   TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 1);
     93   TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 32);
     94   TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 2);
     95   TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 10);
     96   TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 30);
     97   TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 3);
     98   TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 2);
     99   TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 10);
    100   TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 5);
    101   TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 3);
    102   TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 20);
    103   TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 16);
    104   TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 3);
    105   TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 12);
    106   TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 23);
    107   TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 53);
    108   TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 3);
    109   TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 12);
    110 
    111   dump_results_hex (TEST_MSG);
    112 
    113 #ifdef EXTRA_TESTS
    114   EXTRA_TESTS();
    115 #endif
    116 }
    117