1 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s 2 3 #include <arm_neon.h> 4 5 // CHECK-LABEL: define <2 x float> @test_vrnda_f32(<2 x float> %a) #0 { 6 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 7 // CHECK: [[VRNDA_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 8 // CHECK: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> [[VRNDA_V_I]]) #2 9 // CHECK: [[VRNDA_V2_I:%.*]] = bitcast <2 x float> [[VRNDA_V1_I]] to <8 x i8> 10 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDA_V2_I]] to <2 x float> 11 // CHECK: ret <2 x float> [[TMP1]] 12 float32x2_t test_vrnda_f32(float32x2_t a) { 13 return vrnda_f32(a); 14 } 15 16 // CHECK-LABEL: define <4 x float> @test_vrndaq_f32(<4 x float> %a) #0 { 17 // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 18 // CHECK: [[VRNDAQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 19 // CHECK: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> [[VRNDAQ_V_I]]) #2 20 // CHECK: [[VRNDAQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDAQ_V1_I]] to <16 x i8> 21 // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDAQ_V2_I]] to <4 x float> 22 // CHECK: ret <4 x float> [[TMP1]] 23 float32x4_t test_vrndaq_f32(float32x4_t a) { 24 return vrndaq_f32(a); 25 } 26 27 // CHECK-LABEL: define <2 x float> @test_vrndm_f32(<2 x float> %a) #0 { 28 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 29 // CHECK: [[VRNDM_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 30 // CHECK: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> [[VRNDM_V_I]]) #2 31 // CHECK: [[VRNDM_V2_I:%.*]] = bitcast <2 x float> [[VRNDM_V1_I]] to <8 x i8> 32 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDM_V2_I]] to <2 x float> 33 // CHECK: ret <2 x float> [[TMP1]] 34 float32x2_t test_vrndm_f32(float32x2_t a) { 35 return vrndm_f32(a); 36 } 37 38 // CHECK-LABEL: define <4 x float> @test_vrndmq_f32(<4 x float> %a) #0 { 39 // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 40 // CHECK: [[VRNDMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 41 // CHECK: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> [[VRNDMQ_V_I]]) #2 42 // CHECK: [[VRNDMQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDMQ_V1_I]] to <16 x i8> 43 // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDMQ_V2_I]] to <4 x float> 44 // CHECK: ret <4 x float> [[TMP1]] 45 float32x4_t test_vrndmq_f32(float32x4_t a) { 46 return vrndmq_f32(a); 47 } 48 49 // CHECK-LABEL: define <2 x float> @test_vrndn_f32(<2 x float> %a) #0 { 50 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 51 // CHECK: [[VRNDN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 52 // CHECK: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> [[VRNDN_V_I]]) #2 53 // CHECK: [[VRNDN_V2_I:%.*]] = bitcast <2 x float> [[VRNDN_V1_I]] to <8 x i8> 54 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDN_V2_I]] to <2 x float> 55 // CHECK: ret <2 x float> [[TMP1]] 56 float32x2_t test_vrndn_f32(float32x2_t a) { 57 return vrndn_f32(a); 58 } 59 60 // CHECK-LABEL: define <4 x float> @test_vrndnq_f32(<4 x float> %a) #0 { 61 // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 62 // CHECK: [[VRNDNQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 63 // CHECK: [[VRNDNQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintn.v4f32(<4 x float> [[VRNDNQ_V_I]]) #2 64 // CHECK: [[VRNDNQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDNQ_V1_I]] to <16 x i8> 65 // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDNQ_V2_I]] to <4 x float> 66 // CHECK: ret <4 x float> [[TMP1]] 67 float32x4_t test_vrndnq_f32(float32x4_t a) { 68 return vrndnq_f32(a); 69 } 70 71 // CHECK-LABEL: define <2 x float> @test_vrndp_f32(<2 x float> %a) #0 { 72 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 73 // CHECK: [[VRNDP_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 74 // CHECK: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintp.v2f32(<2 x float> [[VRNDP_V_I]]) #2 75 // CHECK: [[VRNDP_V2_I:%.*]] = bitcast <2 x float> [[VRNDP_V1_I]] to <8 x i8> 76 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDP_V2_I]] to <2 x float> 77 // CHECK: ret <2 x float> [[TMP1]] 78 float32x2_t test_vrndp_f32(float32x2_t a) { 79 return vrndp_f32(a); 80 } 81 82 // CHECK-LABEL: define <4 x float> @test_vrndpq_f32(<4 x float> %a) #0 { 83 // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 84 // CHECK: [[VRNDPQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 85 // CHECK: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintp.v4f32(<4 x float> [[VRNDPQ_V_I]]) #2 86 // CHECK: [[VRNDPQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDPQ_V1_I]] to <16 x i8> 87 // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDPQ_V2_I]] to <4 x float> 88 // CHECK: ret <4 x float> [[TMP1]] 89 float32x4_t test_vrndpq_f32(float32x4_t a) { 90 return vrndpq_f32(a); 91 } 92 93 // CHECK-LABEL: define <2 x float> @test_vrndx_f32(<2 x float> %a) #0 { 94 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 95 // CHECK: [[VRNDX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 96 // CHECK: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintx.v2f32(<2 x float> [[VRNDX_V_I]]) #2 97 // CHECK: [[VRNDX_V2_I:%.*]] = bitcast <2 x float> [[VRNDX_V1_I]] to <8 x i8> 98 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDX_V2_I]] to <2 x float> 99 // CHECK: ret <2 x float> [[TMP1]] 100 float32x2_t test_vrndx_f32(float32x2_t a) { 101 return vrndx_f32(a); 102 } 103 104 // CHECK-LABEL: define <4 x float> @test_vrndxq_f32(<4 x float> %a) #0 { 105 // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 106 // CHECK: [[VRNDXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 107 // CHECK: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintx.v4f32(<4 x float> [[VRNDXQ_V_I]]) #2 108 // CHECK: [[VRNDXQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDXQ_V1_I]] to <16 x i8> 109 // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDXQ_V2_I]] to <4 x float> 110 // CHECK: ret <4 x float> [[TMP1]] 111 float32x4_t test_vrndxq_f32(float32x4_t a) { 112 return vrndxq_f32(a); 113 } 114 115 // CHECK-LABEL: define <2 x float> @test_vrnd_f32(<2 x float> %a) #0 { 116 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> 117 // CHECK: [[VRND_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> 118 // CHECK: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintz.v2f32(<2 x float> [[VRND_V_I]]) #2 119 // CHECK: [[VRND_V2_I:%.*]] = bitcast <2 x float> [[VRND_V1_I]] to <8 x i8> 120 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRND_V2_I]] to <2 x float> 121 // CHECK: ret <2 x float> [[TMP1]] 122 float32x2_t test_vrnd_f32(float32x2_t a) { 123 return vrnd_f32(a); 124 } 125 126 // CHECK-LABEL: define <4 x float> @test_vrndq_f32(<4 x float> %a) #0 { 127 // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> 128 // CHECK: [[VRNDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> 129 // CHECK: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintz.v4f32(<4 x float> [[VRNDQ_V_I]]) #2 130 // CHECK: [[VRNDQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDQ_V1_I]] to <16 x i8> 131 // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDQ_V2_I]] to <4 x float> 132 // CHECK: ret <4 x float> [[TMP1]] 133 float32x4_t test_vrndq_f32(float32x4_t a) { 134 return vrndq_f32(a); 135 } 136
