1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 21 /*****************************************************************************/ 22 /* */ 23 /* File Name : ih264d_api.c */ 24 /* */ 25 /* Description : Has all API related functions */ 26 /* */ 27 /* */ 28 /* List of Functions : api_check_struct_sanity */ 29 /* ih264d_set_processor */ 30 /* ih264d_create */ 31 /* ih264d_delete */ 32 /* ih264d_init */ 33 /* ih264d_map_error */ 34 /* ih264d_video_decode */ 35 /* ih264d_get_version */ 36 /* ih264d_get_display_frame */ 37 /* ih264d_set_display_frame */ 38 /* ih264d_set_flush_mode */ 39 /* ih264d_get_status */ 40 /* ih264d_get_buf_info */ 41 /* ih264d_set_params */ 42 /* ih264d_set_default_params */ 43 /* ih264d_reset */ 44 /* ih264d_ctl */ 45 /* ih264d_rel_display_frame */ 46 /* ih264d_set_degrade */ 47 /* ih264d_get_frame_dimensions */ 48 /* ih264d_set_num_cores */ 49 /* ih264d_fill_output_struct_from_context */ 50 /* ih264d_api_function */ 51 /* */ 52 /* Issues / Problems : None */ 53 /* */ 54 /* Revision History : */ 55 /* */ 56 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 57 /* 14 10 2008 100356(SKV) Draft */ 58 /* */ 59 /*****************************************************************************/ 60 #include "ih264_typedefs.h" 61 #include "ih264_macros.h" 62 #include "ih264_platform_macros.h" 63 #include "ih264d_tables.h" 64 #include "iv.h" 65 #include "ivd.h" 66 #include "ih264d.h" 67 #include "ih264d_defs.h" 68 69 #include <string.h> 70 #include <limits.h> 71 #include <stddef.h> 72 73 #include "ih264d_inter_pred.h" 74 75 #include "ih264d_structs.h" 76 #include "ih264d_nal.h" 77 #include "ih264d_error_handler.h" 78 79 #include "ih264d_defs.h" 80 81 #include "ithread.h" 82 #include "ih264d_parse_slice.h" 83 #include "ih264d_function_selector.h" 84 #include "ih264_error.h" 85 #include "ih264_disp_mgr.h" 86 #include "ih264_buf_mgr.h" 87 #include "ih264d_deblocking.h" 88 #include "ih264d_parse_cavlc.h" 89 #include "ih264d_parse_cabac.h" 90 #include "ih264d_utils.h" 91 #include "ih264d_format_conv.h" 92 #include "ih264d_parse_headers.h" 93 #include "ih264d_thread_compute_bs.h" 94 #include <assert.h> 95 96 97 /*********************/ 98 /* Codec Versioning */ 99 /*********************/ 100 //Move this to where it is used 101 #define CODEC_NAME "H264VDEC" 102 #define CODEC_RELEASE_TYPE "production" 103 #define CODEC_RELEASE_VER "05.00" 104 #define CODEC_VENDOR "ITTIAM" 105 #define MAXVERSION_STRLEN 511 106 #ifdef __ANDROID__ 107 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 108 snprintf(version_string, MAXVERSION_STRLEN, \ 109 "@(#)Id:%s_%s Ver:%s Released by %s", \ 110 codec_name, codec_release_type, codec_release_ver, codec_vendor) 111 #else 112 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 113 snprintf(version_string, MAXVERSION_STRLEN, \ 114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \ 115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__) 116 #endif 117 118 119 #define MIN_IN_BUFS 1 120 #define MIN_OUT_BUFS_420 3 121 #define MIN_OUT_BUFS_422ILE 1 122 #define MIN_OUT_BUFS_RGB565 1 123 #define MIN_OUT_BUFS_420SP 2 124 125 #define NUM_FRAMES_LIMIT_ENABLED 0 126 127 #if NUM_FRAMES_LIMIT_ENABLED 128 #define NUM_FRAMES_LIMIT 10000 129 #else 130 #define NUM_FRAMES_LIMIT 0x7FFFFFFF 131 #endif 132 133 134 UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height); 135 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 136 void *pv_api_ip, 137 void *pv_api_op); 138 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl, 139 void *pv_api_ip, 140 void *pv_api_op); 141 142 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op); 143 144 WORD32 ih264d_deblock_display(dec_struct_t *ps_dec); 145 146 void ih264d_signal_decode_thread(dec_struct_t *ps_dec); 147 148 void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec); 149 void ih264d_decode_picture_thread(dec_struct_t *ps_dec); 150 151 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 152 void *pv_api_ip, 153 void *pv_api_op); 154 155 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 156 ivd_video_decode_op_t *ps_dec_op); 157 158 static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 159 void *pv_api_ip, 160 void *pv_api_op) 161 { 162 IVD_API_COMMAND_TYPE_T e_cmd; 163 UWORD32 *pu4_api_ip; 164 UWORD32 *pu4_api_op; 165 UWORD32 i, j; 166 167 if(NULL == pv_api_op) 168 return (IV_FAIL); 169 170 if(NULL == pv_api_ip) 171 return (IV_FAIL); 172 173 pu4_api_ip = (UWORD32 *)pv_api_ip; 174 pu4_api_op = (UWORD32 *)pv_api_op; 175 e_cmd = *(pu4_api_ip + 1); 176 177 /* error checks on handle */ 178 switch((WORD32)e_cmd) 179 { 180 case IVD_CMD_CREATE: 181 break; 182 183 case IVD_CMD_REL_DISPLAY_FRAME: 184 case IVD_CMD_SET_DISPLAY_FRAME: 185 case IVD_CMD_GET_DISPLAY_FRAME: 186 case IVD_CMD_VIDEO_DECODE: 187 case IVD_CMD_DELETE: 188 case IVD_CMD_VIDEO_CTL: 189 if(ps_handle == NULL) 190 { 191 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 192 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 193 return IV_FAIL; 194 } 195 196 if(ps_handle->u4_size != sizeof(iv_obj_t)) 197 { 198 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 199 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 200 return IV_FAIL; 201 } 202 203 if(ps_handle->pv_fxns != ih264d_api_function) 204 { 205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 206 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 207 return IV_FAIL; 208 } 209 210 if(ps_handle->pv_codec_handle == NULL) 211 { 212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 213 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 214 return IV_FAIL; 215 } 216 break; 217 default: 218 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 219 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 220 return IV_FAIL; 221 } 222 223 switch((WORD32)e_cmd) 224 { 225 case IVD_CMD_CREATE: 226 { 227 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip; 228 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op; 229 230 231 ps_op->s_ivd_create_op_t.u4_error_code = 0; 232 233 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t)) 234 || (ps_ip->s_ivd_create_ip_t.u4_size 235 < sizeof(ivd_create_ip_t))) 236 { 237 ps_op->s_ivd_create_op_t.u4_error_code |= 1 238 << IVD_UNSUPPORTEDPARAM; 239 ps_op->s_ivd_create_op_t.u4_error_code |= 240 IVD_IP_API_STRUCT_SIZE_INCORRECT; 241 H264_DEC_DEBUG_PRINT("\n"); 242 return (IV_FAIL); 243 } 244 245 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t)) 246 && (ps_op->s_ivd_create_op_t.u4_size 247 != sizeof(ivd_create_op_t))) 248 { 249 ps_op->s_ivd_create_op_t.u4_error_code |= 1 250 << IVD_UNSUPPORTEDPARAM; 251 ps_op->s_ivd_create_op_t.u4_error_code |= 252 IVD_OP_API_STRUCT_SIZE_INCORRECT; 253 H264_DEC_DEBUG_PRINT("\n"); 254 return (IV_FAIL); 255 } 256 257 258 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P) 259 && (ps_ip->s_ivd_create_ip_t.e_output_format 260 != IV_YUV_422ILE) 261 && (ps_ip->s_ivd_create_ip_t.e_output_format 262 != IV_RGB_565) 263 && (ps_ip->s_ivd_create_ip_t.e_output_format 264 != IV_YUV_420SP_UV) 265 && (ps_ip->s_ivd_create_ip_t.e_output_format 266 != IV_YUV_420SP_VU)) 267 { 268 ps_op->s_ivd_create_op_t.u4_error_code |= 1 269 << IVD_UNSUPPORTEDPARAM; 270 ps_op->s_ivd_create_op_t.u4_error_code |= 271 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 272 H264_DEC_DEBUG_PRINT("\n"); 273 return (IV_FAIL); 274 } 275 276 } 277 break; 278 279 case IVD_CMD_GET_DISPLAY_FRAME: 280 { 281 ih264d_get_display_frame_ip_t *ps_ip = 282 (ih264d_get_display_frame_ip_t *)pv_api_ip; 283 ih264d_get_display_frame_op_t *ps_op = 284 (ih264d_get_display_frame_op_t *)pv_api_op; 285 286 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 287 288 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size 289 != sizeof(ih264d_get_display_frame_ip_t)) 290 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size 291 != sizeof(ivd_get_display_frame_ip_t))) 292 { 293 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 294 << IVD_UNSUPPORTEDPARAM; 295 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 296 IVD_IP_API_STRUCT_SIZE_INCORRECT; 297 return (IV_FAIL); 298 } 299 300 if((ps_op->s_ivd_get_display_frame_op_t.u4_size 301 != sizeof(ih264d_get_display_frame_op_t)) 302 && (ps_op->s_ivd_get_display_frame_op_t.u4_size 303 != sizeof(ivd_get_display_frame_op_t))) 304 { 305 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 306 << IVD_UNSUPPORTEDPARAM; 307 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 308 IVD_OP_API_STRUCT_SIZE_INCORRECT; 309 return (IV_FAIL); 310 } 311 } 312 break; 313 314 case IVD_CMD_REL_DISPLAY_FRAME: 315 { 316 ih264d_rel_display_frame_ip_t *ps_ip = 317 (ih264d_rel_display_frame_ip_t *)pv_api_ip; 318 ih264d_rel_display_frame_op_t *ps_op = 319 (ih264d_rel_display_frame_op_t *)pv_api_op; 320 321 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 322 323 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 324 != sizeof(ih264d_rel_display_frame_ip_t)) 325 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 326 != sizeof(ivd_rel_display_frame_ip_t))) 327 { 328 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 329 << IVD_UNSUPPORTEDPARAM; 330 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 331 IVD_IP_API_STRUCT_SIZE_INCORRECT; 332 return (IV_FAIL); 333 } 334 335 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size 336 != sizeof(ih264d_rel_display_frame_op_t)) 337 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size 338 != sizeof(ivd_rel_display_frame_op_t))) 339 { 340 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 341 << IVD_UNSUPPORTEDPARAM; 342 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 343 IVD_OP_API_STRUCT_SIZE_INCORRECT; 344 return (IV_FAIL); 345 } 346 347 } 348 break; 349 350 case IVD_CMD_SET_DISPLAY_FRAME: 351 { 352 ih264d_set_display_frame_ip_t *ps_ip = 353 (ih264d_set_display_frame_ip_t *)pv_api_ip; 354 ih264d_set_display_frame_op_t *ps_op = 355 (ih264d_set_display_frame_op_t *)pv_api_op; 356 UWORD32 j; 357 358 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 359 360 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size 361 != sizeof(ih264d_set_display_frame_ip_t)) 362 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size 363 != sizeof(ivd_set_display_frame_ip_t))) 364 { 365 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 366 << IVD_UNSUPPORTEDPARAM; 367 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 368 IVD_IP_API_STRUCT_SIZE_INCORRECT; 369 return (IV_FAIL); 370 } 371 372 if((ps_op->s_ivd_set_display_frame_op_t.u4_size 373 != sizeof(ih264d_set_display_frame_op_t)) 374 && (ps_op->s_ivd_set_display_frame_op_t.u4_size 375 != sizeof(ivd_set_display_frame_op_t))) 376 { 377 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 378 << IVD_UNSUPPORTEDPARAM; 379 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 380 IVD_OP_API_STRUCT_SIZE_INCORRECT; 381 return (IV_FAIL); 382 } 383 384 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 385 { 386 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 387 << IVD_UNSUPPORTEDPARAM; 388 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 389 IVD_DISP_FRM_ZERO_OP_BUFS; 390 return IV_FAIL; 391 } 392 393 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; 394 j++) 395 { 396 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs 397 == 0) 398 { 399 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 400 << IVD_UNSUPPORTEDPARAM; 401 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 402 IVD_DISP_FRM_ZERO_OP_BUFS; 403 return IV_FAIL; 404 } 405 406 for(i = 0; 407 i 408 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs; 409 i++) 410 { 411 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] 412 == NULL) 413 { 414 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 415 << IVD_UNSUPPORTEDPARAM; 416 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 417 IVD_DISP_FRM_OP_BUF_NULL; 418 return IV_FAIL; 419 } 420 421 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] 422 == 0) 423 { 424 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 425 << IVD_UNSUPPORTEDPARAM; 426 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 427 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 428 return IV_FAIL; 429 } 430 } 431 } 432 } 433 break; 434 435 case IVD_CMD_VIDEO_DECODE: 436 { 437 ih264d_video_decode_ip_t *ps_ip = 438 (ih264d_video_decode_ip_t *)pv_api_ip; 439 ih264d_video_decode_op_t *ps_op = 440 (ih264d_video_decode_op_t *)pv_api_op; 441 442 H264_DEC_DEBUG_PRINT("The input bytes is: %d", 443 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes); 444 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 445 446 if(ps_ip->s_ivd_video_decode_ip_t.u4_size 447 != sizeof(ih264d_video_decode_ip_t)&& 448 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer)) 449 { 450 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 451 << IVD_UNSUPPORTEDPARAM; 452 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 453 IVD_IP_API_STRUCT_SIZE_INCORRECT; 454 return (IV_FAIL); 455 } 456 457 if(ps_op->s_ivd_video_decode_op_t.u4_size 458 != sizeof(ih264d_video_decode_op_t)&& 459 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present)) 460 { 461 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 462 << IVD_UNSUPPORTEDPARAM; 463 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 464 IVD_OP_API_STRUCT_SIZE_INCORRECT; 465 return (IV_FAIL); 466 } 467 468 } 469 break; 470 471 case IVD_CMD_DELETE: 472 { 473 ih264d_delete_ip_t *ps_ip = 474 (ih264d_delete_ip_t *)pv_api_ip; 475 ih264d_delete_op_t *ps_op = 476 (ih264d_delete_op_t *)pv_api_op; 477 478 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 479 480 if(ps_ip->s_ivd_delete_ip_t.u4_size 481 != sizeof(ih264d_delete_ip_t)) 482 { 483 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 484 << IVD_UNSUPPORTEDPARAM; 485 ps_op->s_ivd_delete_op_t.u4_error_code |= 486 IVD_IP_API_STRUCT_SIZE_INCORRECT; 487 return (IV_FAIL); 488 } 489 490 if(ps_op->s_ivd_delete_op_t.u4_size 491 != sizeof(ih264d_delete_op_t)) 492 { 493 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 494 << IVD_UNSUPPORTEDPARAM; 495 ps_op->s_ivd_delete_op_t.u4_error_code |= 496 IVD_OP_API_STRUCT_SIZE_INCORRECT; 497 return (IV_FAIL); 498 } 499 500 } 501 break; 502 503 case IVD_CMD_VIDEO_CTL: 504 { 505 UWORD32 *pu4_ptr_cmd; 506 UWORD32 sub_command; 507 508 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 509 pu4_ptr_cmd += 2; 510 sub_command = *pu4_ptr_cmd; 511 512 switch(sub_command) 513 { 514 case IVD_CMD_CTL_SETPARAMS: 515 { 516 ih264d_ctl_set_config_ip_t *ps_ip; 517 ih264d_ctl_set_config_op_t *ps_op; 518 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip; 519 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 520 521 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size 522 != sizeof(ih264d_ctl_set_config_ip_t)) 523 { 524 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 525 << IVD_UNSUPPORTEDPARAM; 526 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 527 IVD_IP_API_STRUCT_SIZE_INCORRECT; 528 return IV_FAIL; 529 } 530 } 531 //no break; is needed here 532 case IVD_CMD_CTL_SETDEFAULT: 533 { 534 ih264d_ctl_set_config_op_t *ps_op; 535 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 536 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size 537 != sizeof(ih264d_ctl_set_config_op_t)) 538 { 539 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 540 << IVD_UNSUPPORTEDPARAM; 541 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 542 IVD_OP_API_STRUCT_SIZE_INCORRECT; 543 return IV_FAIL; 544 } 545 } 546 break; 547 548 case IVD_CMD_CTL_GETPARAMS: 549 { 550 ih264d_ctl_getstatus_ip_t *ps_ip; 551 ih264d_ctl_getstatus_op_t *ps_op; 552 553 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip; 554 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op; 555 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size 556 != sizeof(ih264d_ctl_getstatus_ip_t)) 557 { 558 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 559 << IVD_UNSUPPORTEDPARAM; 560 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 561 IVD_IP_API_STRUCT_SIZE_INCORRECT; 562 return IV_FAIL; 563 } 564 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size 565 != sizeof(ih264d_ctl_getstatus_op_t)) 566 { 567 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 568 << IVD_UNSUPPORTEDPARAM; 569 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 570 IVD_OP_API_STRUCT_SIZE_INCORRECT; 571 return IV_FAIL; 572 } 573 } 574 break; 575 576 case IVD_CMD_CTL_GETBUFINFO: 577 { 578 ih264d_ctl_getbufinfo_ip_t *ps_ip; 579 ih264d_ctl_getbufinfo_op_t *ps_op; 580 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip; 581 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op; 582 583 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size 584 != sizeof(ih264d_ctl_getbufinfo_ip_t)) 585 { 586 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 587 << IVD_UNSUPPORTEDPARAM; 588 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 589 IVD_IP_API_STRUCT_SIZE_INCORRECT; 590 return IV_FAIL; 591 } 592 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size 593 != sizeof(ih264d_ctl_getbufinfo_op_t)) 594 { 595 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 596 << IVD_UNSUPPORTEDPARAM; 597 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 598 IVD_OP_API_STRUCT_SIZE_INCORRECT; 599 return IV_FAIL; 600 } 601 } 602 break; 603 604 case IVD_CMD_CTL_GETVERSION: 605 { 606 ih264d_ctl_getversioninfo_ip_t *ps_ip; 607 ih264d_ctl_getversioninfo_op_t *ps_op; 608 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip; 609 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op; 610 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size 611 != sizeof(ih264d_ctl_getversioninfo_ip_t)) 612 { 613 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 614 << IVD_UNSUPPORTEDPARAM; 615 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 616 IVD_IP_API_STRUCT_SIZE_INCORRECT; 617 return IV_FAIL; 618 } 619 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size 620 != sizeof(ih264d_ctl_getversioninfo_op_t)) 621 { 622 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 623 << IVD_UNSUPPORTEDPARAM; 624 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 625 IVD_OP_API_STRUCT_SIZE_INCORRECT; 626 return IV_FAIL; 627 } 628 } 629 break; 630 631 case IVD_CMD_CTL_FLUSH: 632 { 633 ih264d_ctl_flush_ip_t *ps_ip; 634 ih264d_ctl_flush_op_t *ps_op; 635 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip; 636 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op; 637 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size 638 != sizeof(ih264d_ctl_flush_ip_t)) 639 { 640 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 641 << IVD_UNSUPPORTEDPARAM; 642 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 643 IVD_IP_API_STRUCT_SIZE_INCORRECT; 644 return IV_FAIL; 645 } 646 if(ps_op->s_ivd_ctl_flush_op_t.u4_size 647 != sizeof(ih264d_ctl_flush_op_t)) 648 { 649 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 650 << IVD_UNSUPPORTEDPARAM; 651 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 652 IVD_OP_API_STRUCT_SIZE_INCORRECT; 653 return IV_FAIL; 654 } 655 } 656 break; 657 658 case IVD_CMD_CTL_RESET: 659 { 660 ih264d_ctl_reset_ip_t *ps_ip; 661 ih264d_ctl_reset_op_t *ps_op; 662 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip; 663 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op; 664 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size 665 != sizeof(ih264d_ctl_reset_ip_t)) 666 { 667 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 668 << IVD_UNSUPPORTEDPARAM; 669 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 670 IVD_IP_API_STRUCT_SIZE_INCORRECT; 671 return IV_FAIL; 672 } 673 if(ps_op->s_ivd_ctl_reset_op_t.u4_size 674 != sizeof(ih264d_ctl_reset_op_t)) 675 { 676 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 677 << IVD_UNSUPPORTEDPARAM; 678 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 679 IVD_OP_API_STRUCT_SIZE_INCORRECT; 680 return IV_FAIL; 681 } 682 } 683 break; 684 685 case IH264D_CMD_CTL_DEGRADE: 686 { 687 ih264d_ctl_degrade_ip_t *ps_ip; 688 ih264d_ctl_degrade_op_t *ps_op; 689 690 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 691 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 692 693 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t)) 694 { 695 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 696 ps_op->u4_error_code |= 697 IVD_IP_API_STRUCT_SIZE_INCORRECT; 698 return IV_FAIL; 699 } 700 701 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t)) 702 { 703 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 704 ps_op->u4_error_code |= 705 IVD_OP_API_STRUCT_SIZE_INCORRECT; 706 return IV_FAIL; 707 } 708 709 if((ps_ip->i4_degrade_pics < 0) 710 || (ps_ip->i4_degrade_pics > 4) 711 || (ps_ip->i4_nondegrade_interval < 0) 712 || (ps_ip->i4_degrade_type < 0) 713 || (ps_ip->i4_degrade_type > 15)) 714 { 715 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 716 return IV_FAIL; 717 } 718 719 break; 720 } 721 722 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 723 { 724 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 725 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 726 727 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 728 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 729 730 if(ps_ip->u4_size 731 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t)) 732 { 733 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 734 ps_op->u4_error_code |= 735 IVD_IP_API_STRUCT_SIZE_INCORRECT; 736 return IV_FAIL; 737 } 738 739 if(ps_op->u4_size 740 != sizeof(ih264d_ctl_get_frame_dimensions_op_t)) 741 { 742 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 743 ps_op->u4_error_code |= 744 IVD_OP_API_STRUCT_SIZE_INCORRECT; 745 return IV_FAIL; 746 } 747 748 break; 749 } 750 case IH264D_CMD_CTL_GET_VUI_PARAMS: 751 { 752 ih264d_ctl_get_vui_params_ip_t *ps_ip; 753 ih264d_ctl_get_vui_params_op_t *ps_op; 754 755 ps_ip = 756 (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip; 757 ps_op = 758 (ih264d_ctl_get_vui_params_op_t *)pv_api_op; 759 760 if(ps_ip->u4_size 761 != sizeof(ih264d_ctl_get_vui_params_ip_t)) 762 { 763 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 764 ps_op->u4_error_code |= 765 IVD_IP_API_STRUCT_SIZE_INCORRECT; 766 return IV_FAIL; 767 } 768 769 if(ps_op->u4_size 770 != sizeof(ih264d_ctl_get_vui_params_op_t)) 771 { 772 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 773 ps_op->u4_error_code |= 774 IVD_OP_API_STRUCT_SIZE_INCORRECT; 775 return IV_FAIL; 776 } 777 778 break; 779 } 780 case IH264D_CMD_CTL_SET_NUM_CORES: 781 { 782 ih264d_ctl_set_num_cores_ip_t *ps_ip; 783 ih264d_ctl_set_num_cores_op_t *ps_op; 784 785 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 786 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 787 788 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t)) 789 { 790 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 791 ps_op->u4_error_code |= 792 IVD_IP_API_STRUCT_SIZE_INCORRECT; 793 return IV_FAIL; 794 } 795 796 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t)) 797 { 798 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 799 ps_op->u4_error_code |= 800 IVD_OP_API_STRUCT_SIZE_INCORRECT; 801 return IV_FAIL; 802 } 803 804 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2) 805 && (ps_ip->u4_num_cores != 3) 806 && (ps_ip->u4_num_cores != 4)) 807 { 808 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 809 return IV_FAIL; 810 } 811 break; 812 } 813 case IH264D_CMD_CTL_SET_PROCESSOR: 814 { 815 ih264d_ctl_set_processor_ip_t *ps_ip; 816 ih264d_ctl_set_processor_op_t *ps_op; 817 818 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 819 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 820 821 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t)) 822 { 823 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 824 ps_op->u4_error_code |= 825 IVD_IP_API_STRUCT_SIZE_INCORRECT; 826 return IV_FAIL; 827 } 828 829 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t)) 830 { 831 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 832 ps_op->u4_error_code |= 833 IVD_OP_API_STRUCT_SIZE_INCORRECT; 834 return IV_FAIL; 835 } 836 837 break; 838 } 839 default: 840 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 841 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 842 return IV_FAIL; 843 break; 844 } 845 } 846 break; 847 } 848 849 return IV_SUCCESS; 850 } 851 852 853 /** 854 ******************************************************************************* 855 * 856 * @brief 857 * Sets Processor type 858 * 859 * @par Description: 860 * Sets Processor type 861 * 862 * @param[in] ps_codec_obj 863 * Pointer to codec object at API level 864 * 865 * @param[in] pv_api_ip 866 * Pointer to input argument structure 867 * 868 * @param[out] pv_api_op 869 * Pointer to output argument structure 870 * 871 * @returns Status 872 * 873 * @remarks 874 * 875 * 876 ******************************************************************************* 877 */ 878 879 WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 880 { 881 ih264d_ctl_set_processor_ip_t *ps_ip; 882 ih264d_ctl_set_processor_op_t *ps_op; 883 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle; 884 885 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 886 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 887 888 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 889 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 890 891 ih264d_init_function_ptr(ps_codec); 892 893 ps_op->u4_error_code = 0; 894 return IV_SUCCESS; 895 } 896 897 898 /************************************************************************** 899 * \if Function name : ih264d_init_decoder \endif 900 * 901 * 902 * \brief 903 * Initializes the decoder 904 * 905 * \param apiVersion : Version of the api being used. 906 * \param errorHandlingMechanism : Mechanism to be used for errror handling. 907 * \param postFilteringType: Type of post filtering operation to be used. 908 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0]. 909 * \param uc_dispBufs: Number of Display Buffers. 910 * \param p_NALBufAPI: Pointer to NAL Buffer API. 911 * \param p_DispBufAPI: Pointer to Display Buffer API. 912 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 913 * for memory allocation and freeing. 914 * 915 * \return 916 * 0 on Success and -1 on error 917 * 918 ************************************************************************** 919 */ 920 void ih264d_init_decoder(void * ps_dec_params) 921 { 922 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params; 923 dec_slice_params_t *ps_cur_slice; 924 pocstruct_t *ps_prev_poc, *ps_cur_poc; 925 WORD32 size; 926 927 size = sizeof(pred_info_t) * 2 * 32; 928 memset(ps_dec->ps_pred, 0 , size); 929 930 size = sizeof(disp_mgr_t); 931 memset(ps_dec->pv_disp_buf_mgr, 0 , size); 932 933 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 934 memset(ps_dec->pv_pic_buf_mgr, 0, size); 935 936 size = sizeof(dec_err_status_t); 937 memset(ps_dec->ps_dec_err_status, 0, size); 938 939 size = sizeof(sei); 940 memset(ps_dec->ps_sei, 0, size); 941 942 size = sizeof(dpb_commands_t); 943 memset(ps_dec->ps_dpb_cmds, 0, size); 944 945 size = sizeof(dec_bit_stream_t); 946 memset(ps_dec->ps_bitstrm, 0, size); 947 948 size = sizeof(dec_slice_params_t); 949 memset(ps_dec->ps_cur_slice, 0, size); 950 951 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 952 memset(ps_dec->pv_scratch_sps_pps, 0, size); 953 954 size = sizeof(ctxt_inc_mb_info_t); 955 memset(ps_dec->ps_left_mb_ctxt_info, 0, size); 956 957 size = (sizeof(neighbouradd_t) << 2); 958 memset(ps_dec->ps_left_mvpred_addr, 0 ,size); 959 960 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 961 memset(ps_dec->pv_mv_buf_mgr, 0, size); 962 963 /* Free any dynamic buffers that are allocated */ 964 ih264d_free_dynamic_bufs(ps_dec); 965 966 ps_cur_slice = ps_dec->ps_cur_slice; 967 ps_dec->init_done = 0; 968 969 ps_dec->u4_num_cores = 1; 970 971 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0; 972 973 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE; 974 ps_dec->u4_app_disable_deblk_frm = 0; 975 ps_dec->i4_degrade_type = 0; 976 ps_dec->i4_degrade_pics = 0; 977 978 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE; 979 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE; 980 981 memset(ps_dec->ps_pps, 0, 982 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS)); 983 memset(ps_dec->ps_sps, 0, 984 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS)); 985 986 /* Initialization of function pointers ih264d_deblock_picture function*/ 987 988 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff; 989 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff; 990 991 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec; 992 993 ps_dec->u4_num_fld_in_frm = 0; 994 995 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 996 997 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/ 998 ps_dec->ps_sei->u1_is_valid = 0; 999 1000 /* decParams Initializations */ 1001 ps_dec->ps_cur_pps = NULL; 1002 ps_dec->ps_cur_sps = NULL; 1003 ps_dec->u1_init_dec_flag = 0; 1004 ps_dec->u1_first_slice_in_stream = 1; 1005 ps_dec->u1_last_pic_not_decoded = 0; 1006 ps_dec->u4_app_disp_width = 0; 1007 ps_dec->i4_header_decoded = 0; 1008 ps_dec->u4_total_frames_decoded = 0; 1009 1010 ps_dec->i4_error_code = 0; 1011 ps_dec->i4_content_type = -1; 1012 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0; 1013 1014 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS; 1015 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN; 1016 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT; 1017 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME; 1018 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN; 1019 1020 ps_dec->u1_pr_sl_type = 0xFF; 1021 ps_dec->u2_mbx = 0xffff; 1022 ps_dec->u2_mby = 0; 1023 ps_dec->u2_total_mbs_coded = 0; 1024 1025 /* POC initializations */ 1026 ps_prev_poc = &ps_dec->s_prev_pic_poc; 1027 ps_cur_poc = &ps_dec->s_cur_pic_poc; 1028 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0; 1029 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0; 1030 ps_prev_poc->i4_delta_pic_order_cnt_bottom = 1031 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0; 1032 ps_prev_poc->i4_delta_pic_order_cnt[0] = 1033 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 1034 ps_prev_poc->i4_delta_pic_order_cnt[1] = 1035 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 1036 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1037 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 1038 0; 1039 ps_prev_poc->i4_bottom_field_order_count = 1040 ps_cur_poc->i4_bottom_field_order_count = 0; 1041 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0; 1042 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1043 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0; 1044 ps_cur_slice->u1_mmco_equalto5 = 0; 1045 ps_cur_slice->u2_frame_num = 0; 1046 1047 ps_dec->i4_max_poc = 0; 1048 ps_dec->i4_prev_max_display_seq = 0; 1049 ps_dec->u1_recon_mb_grp = 4; 1050 1051 /* Field PIC initializations */ 1052 ps_dec->u1_second_field = 0; 1053 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0; 1054 1055 /* Set the cropping parameters as zero */ 1056 ps_dec->u2_crop_offset_y = 0; 1057 ps_dec->u2_crop_offset_uv = 0; 1058 1059 /* The Initial Frame Rate Info is not Present */ 1060 ps_dec->i4_vui_frame_rate = -1; 1061 ps_dec->i4_pic_type = -1; 1062 ps_dec->i4_frametype = -1; 1063 ps_dec->i4_content_type = -1; 1064 1065 ps_dec->u1_res_changed = 0; 1066 1067 1068 ps_dec->u1_frame_decoded_flag = 0; 1069 1070 /* Set the default frame seek mask mode */ 1071 ps_dec->u4_skip_frm_mask = SKIP_NONE; 1072 1073 /********************************************************/ 1074 /* Initialize CAVLC residual decoding function pointers */ 1075 /********************************************************/ 1076 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1; 1077 ps_dec->pf_cavlc_4x4res_block[1] = 1078 ih264d_cavlc_4x4res_block_totalcoeff_2to10; 1079 ps_dec->pf_cavlc_4x4res_block[2] = 1080 ih264d_cavlc_4x4res_block_totalcoeff_11to16; 1081 1082 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7; 1083 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8; 1084 1085 ps_dec->pf_cavlc_parse_8x8block[0] = 1086 ih264d_cavlc_parse_8x8block_none_available; 1087 ps_dec->pf_cavlc_parse_8x8block[1] = 1088 ih264d_cavlc_parse_8x8block_left_available; 1089 ps_dec->pf_cavlc_parse_8x8block[2] = 1090 ih264d_cavlc_parse_8x8block_top_available; 1091 ps_dec->pf_cavlc_parse_8x8block[3] = 1092 ih264d_cavlc_parse_8x8block_both_available; 1093 1094 /***************************************************************************/ 1095 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */ 1096 /***************************************************************************/ 1097 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice; 1098 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice; 1099 1100 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice; 1101 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice; 1102 1103 ps_dec->pf_fill_bs_xtra_left_edge[0] = 1104 ih264d_fill_bs_xtra_left_edge_cur_frm; 1105 ps_dec->pf_fill_bs_xtra_left_edge[1] = 1106 ih264d_fill_bs_xtra_left_edge_cur_fld; 1107 1108 /* Initialize Reference Pic Buffers */ 1109 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr); 1110 1111 ps_dec->u2_prv_frame_num = 0; 1112 ps_dec->u1_top_bottom_decoded = 0; 1113 ps_dec->u1_dangling_field = 0; 1114 1115 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table; 1116 1117 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0]; 1118 ps_dec->pi1_left_ref_idx_ctxt_inc = 1119 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0]; 1120 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb; 1121 1122 /* ! */ 1123 /* Initializing flush frame u4_flag */ 1124 ps_dec->u1_flushfrm = 0; 1125 1126 { 1127 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec; 1128 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec; 1129 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec; 1130 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec; 1131 } 1132 1133 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 1134 memset(ps_dec->u4_disp_buf_mapping, 0, 1135 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1136 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1137 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1138 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t)); 1139 1140 ih264d_init_arch(ps_dec); 1141 ih264d_init_function_ptr(ps_dec); 1142 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 1143 ps_dec->init_done = 1; 1144 1145 } 1146 WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl) 1147 { 1148 dec_struct_t *ps_dec; 1149 1150 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1151 void *pv_mem_ctxt; 1152 1153 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle; 1154 pf_aligned_free = ps_dec->pf_aligned_free; 1155 pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1156 1157 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps); 1158 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps); 1159 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle); 1160 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle); 1161 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr); 1162 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred); 1163 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr); 1164 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr); 1165 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base); 1166 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status); 1167 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei); 1168 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds); 1169 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm); 1170 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice); 1171 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps); 1172 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static); 1173 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base); 1174 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t); 1175 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info); 1176 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base); 1177 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1); 1178 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer); 1179 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base); 1180 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat); 1181 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat); 1182 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr); 1183 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr); 1184 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base); 1185 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle); 1186 1187 if(dec_hdl) 1188 { 1189 pf_aligned_free(pv_mem_ctxt, dec_hdl); 1190 } 1191 return IV_SUCCESS; 1192 } 1193 /*****************************************************************************/ 1194 /* */ 1195 /* Function Name : ih264d_create */ 1196 /* */ 1197 /* Description : creates decoder */ 1198 /* */ 1199 /* Inputs :iv_obj_t decoder handle */ 1200 /* :pv_api_ip pointer to input structure */ 1201 /* :pv_api_op pointer to output structure */ 1202 /* Outputs : */ 1203 /* Returns : void */ 1204 /* */ 1205 /* Issues : none */ 1206 /* */ 1207 /* Revision History: */ 1208 /* */ 1209 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1210 /* 22 10 2008 100356 Draft */ 1211 /* */ 1212 /*****************************************************************************/ 1213 WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op) 1214 { 1215 ih264d_create_ip_t *ps_create_ip; 1216 ih264d_create_op_t *ps_create_op; 1217 void *pv_buf; 1218 UWORD8 *pu1_buf; 1219 dec_struct_t *ps_dec; 1220 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size); 1221 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1222 void *pv_mem_ctxt; 1223 WORD32 size; 1224 1225 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip; 1226 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1227 1228 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1229 1230 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc; 1231 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free; 1232 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt; 1233 1234 /* Initialize return handle to NULL */ 1235 ps_create_op->s_ivd_create_op_t.pv_handle = NULL; 1236 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t)); 1237 RETURN_IF((NULL == pv_buf), IV_FAIL); 1238 *dec_hdl = (iv_obj_t *)pv_buf; 1239 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl; 1240 1241 (*dec_hdl)->pv_codec_handle = NULL; 1242 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t)); 1243 RETURN_IF((NULL == pv_buf), IV_FAIL); 1244 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf; 1245 ps_dec = (dec_struct_t *)pv_buf; 1246 1247 memset(ps_dec, 0, sizeof(dec_struct_t)); 1248 1249 #ifndef LOGO_EN 1250 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf; 1251 #else 1252 ps_dec->u4_share_disp_buf = 0; 1253 #endif 1254 1255 ps_dec->u1_chroma_format = 1256 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format); 1257 1258 if((ps_dec->u1_chroma_format != IV_YUV_420P) 1259 && (ps_dec->u1_chroma_format 1260 != IV_YUV_420SP_UV) 1261 && (ps_dec->u1_chroma_format 1262 != IV_YUV_420SP_VU)) 1263 { 1264 ps_dec->u4_share_disp_buf = 0; 1265 } 1266 1267 ps_dec->pf_aligned_alloc = pf_aligned_alloc; 1268 ps_dec->pf_aligned_free = pf_aligned_free; 1269 ps_dec->pv_mem_ctxt = pv_mem_ctxt; 1270 1271 1272 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS); 1273 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1274 RETURN_IF((NULL == pv_buf), IV_FAIL); 1275 ps_dec->ps_sps = pv_buf; 1276 1277 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS; 1278 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1279 RETURN_IF((NULL == pv_buf), IV_FAIL); 1280 ps_dec->ps_pps = pv_buf; 1281 1282 size = ithread_get_handle_size(); 1283 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1284 RETURN_IF((NULL == pv_buf), IV_FAIL); 1285 ps_dec->pv_dec_thread_handle = pv_buf; 1286 1287 size = ithread_get_handle_size(); 1288 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1289 RETURN_IF((NULL == pv_buf), IV_FAIL); 1290 ps_dec->pv_bs_deblk_thread_handle = pv_buf; 1291 1292 size = sizeof(dpb_manager_t); 1293 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1294 RETURN_IF((NULL == pv_buf), IV_FAIL); 1295 ps_dec->ps_dpb_mgr = pv_buf; 1296 1297 size = sizeof(pred_info_t) * 2 * 32; 1298 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1299 RETURN_IF((NULL == pv_buf), IV_FAIL); 1300 ps_dec->ps_pred = pv_buf; 1301 1302 size = sizeof(disp_mgr_t); 1303 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1304 RETURN_IF((NULL == pv_buf), IV_FAIL); 1305 ps_dec->pv_disp_buf_mgr = pv_buf; 1306 1307 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1308 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1309 RETURN_IF((NULL == pv_buf), IV_FAIL); 1310 ps_dec->pv_pic_buf_mgr = pv_buf; 1311 1312 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2); 1313 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1314 RETURN_IF((NULL == pv_buf), IV_FAIL); 1315 ps_dec->ps_pic_buf_base = pv_buf; 1316 1317 size = sizeof(dec_err_status_t); 1318 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1319 RETURN_IF((NULL == pv_buf), IV_FAIL); 1320 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf; 1321 1322 size = sizeof(sei); 1323 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1324 RETURN_IF((NULL == pv_buf), IV_FAIL); 1325 ps_dec->ps_sei = (sei *)pv_buf; 1326 1327 size = sizeof(dpb_commands_t); 1328 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1329 RETURN_IF((NULL == pv_buf), IV_FAIL); 1330 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf; 1331 1332 size = sizeof(dec_bit_stream_t); 1333 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1334 RETURN_IF((NULL == pv_buf), IV_FAIL); 1335 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf; 1336 1337 size = sizeof(dec_slice_params_t); 1338 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1339 RETURN_IF((NULL == pv_buf), IV_FAIL); 1340 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf; 1341 1342 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 1343 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1344 RETURN_IF((NULL == pv_buf), IV_FAIL); 1345 ps_dec->pv_scratch_sps_pps = pv_buf; 1346 1347 1348 ps_dec->u4_static_bits_buf_size = 256000; 1349 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size); 1350 RETURN_IF((NULL == pv_buf), IV_FAIL); 1351 ps_dec->pu1_bits_buf_static = pv_buf; 1352 1353 1354 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) 1355 * sizeof(void *)); 1356 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1357 RETURN_IF((NULL == pv_buf), IV_FAIL); 1358 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf; 1359 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size); 1360 1361 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC; 1362 1363 1364 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 1365 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1366 RETURN_IF((NULL == pv_buf), IV_FAIL); 1367 ps_dec->p_cabac_ctxt_table_t = pv_buf; 1368 1369 1370 1371 size = sizeof(ctxt_inc_mb_info_t); 1372 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1373 RETURN_IF((NULL == pv_buf), IV_FAIL); 1374 ps_dec->ps_left_mb_ctxt_info = pv_buf; 1375 1376 1377 1378 size = MAX_REF_BUF_SIZE * 2; 1379 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1380 RETURN_IF((NULL == pv_buf), IV_FAIL); 1381 ps_dec->pu1_ref_buff_base = pv_buf; 1382 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE; 1383 1384 1385 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 1386 * PRED_BUFFER_HEIGHT * 2); 1387 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1388 RETURN_IF((NULL == pv_buf), IV_FAIL); 1389 ps_dec->pi2_pred1 = pv_buf; 1390 1391 1392 size = sizeof(UWORD8) * (MB_LUM_SIZE); 1393 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1394 RETURN_IF((NULL == pv_buf), IV_FAIL); 1395 ps_dec->pu1_temp_mc_buffer = pv_buf; 1396 1397 1398 1399 1400 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 1401 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1402 RETURN_IF((NULL == pv_buf), IV_FAIL); 1403 1404 ps_dec->pu1_init_dpb_base = pv_buf; 1405 pu1_buf = pv_buf; 1406 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf; 1407 1408 pu1_buf += size / 2; 1409 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf; 1410 1411 size = (sizeof(UWORD32) * 2 * 3 1412 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2); 1413 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1414 RETURN_IF((NULL == pv_buf), IV_FAIL); 1415 ps_dec->pu4_mbaff_wt_mat = pv_buf; 1416 1417 size = sizeof(UWORD32) * 2 * 3 1418 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)); 1419 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1420 RETURN_IF((NULL == pv_buf), IV_FAIL); 1421 ps_dec->pu4_wts_ofsts_mat = pv_buf; 1422 1423 1424 size = (sizeof(neighbouradd_t) << 2); 1425 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1426 RETURN_IF((NULL == pv_buf), IV_FAIL); 1427 ps_dec->ps_left_mvpred_addr = pv_buf; 1428 1429 1430 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1431 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1432 RETURN_IF((NULL == pv_buf), IV_FAIL); 1433 ps_dec->pv_mv_buf_mgr = pv_buf; 1434 1435 1436 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 1437 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1438 RETURN_IF((NULL == pv_buf), IV_FAIL); 1439 ps_dec->ps_col_mv_base = pv_buf; 1440 memset(ps_dec->ps_col_mv_base, 0, size); 1441 1442 { 1443 UWORD8 i; 1444 struct pic_buffer_t *ps_init_dpb; 1445 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0]; 1446 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1447 { 1448 ps_init_dpb->pu1_buf1 = NULL; 1449 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1450 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb; 1451 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb; 1452 ps_init_dpb++; 1453 } 1454 1455 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0]; 1456 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1457 { 1458 ps_init_dpb->pu1_buf1 = NULL; 1459 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1460 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb; 1461 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb; 1462 ps_init_dpb++; 1463 } 1464 } 1465 ih264d_init_decoder(ps_dec); 1466 1467 return IV_SUCCESS; 1468 } 1469 1470 1471 /*****************************************************************************/ 1472 /* */ 1473 /* Function Name : ih264d_create */ 1474 /* */ 1475 /* Description : creates decoder */ 1476 /* */ 1477 /* Inputs :iv_obj_t decoder handle */ 1478 /* :pv_api_ip pointer to input structure */ 1479 /* :pv_api_op pointer to output structure */ 1480 /* Outputs : */ 1481 /* Returns : void */ 1482 /* */ 1483 /* Issues : none */ 1484 /* */ 1485 /* Revision History: */ 1486 /* */ 1487 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1488 /* 22 10 2008 100356 Draft */ 1489 /* */ 1490 /*****************************************************************************/ 1491 WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1492 { 1493 ih264d_create_op_t *ps_create_op; 1494 1495 WORD32 ret; 1496 1497 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1498 1499 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1500 1501 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op); 1502 1503 /* If allocation of some buffer fails, then free buffers allocated till then */ 1504 if((IV_FAIL == ret) && (NULL != dec_hdl)) 1505 { 1506 ih264d_free_static_bufs(dec_hdl); 1507 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED; 1508 ps_create_op->s_ivd_create_op_t.u4_error_code = 1 << IVD_FATALERROR; 1509 1510 return IV_FAIL; 1511 } 1512 1513 return IV_SUCCESS; 1514 } 1515 1516 /*****************************************************************************/ 1517 /* */ 1518 /* Function Name : ih264d_map_error */ 1519 /* */ 1520 /* Description : Maps error codes to IVD error groups */ 1521 /* */ 1522 /* Inputs : */ 1523 /* Globals : <Does it use any global variables?> */ 1524 /* Outputs : */ 1525 /* Returns : void */ 1526 /* */ 1527 /* Issues : none */ 1528 /* */ 1529 /* Revision History: */ 1530 /* */ 1531 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1532 /* 22 10 2008 100356 Draft */ 1533 /* */ 1534 /*****************************************************************************/ 1535 UWORD32 ih264d_map_error(UWORD32 i4_err_status) 1536 { 1537 UWORD32 temp = 0; 1538 1539 switch(i4_err_status) 1540 { 1541 case ERROR_MEM_ALLOC_ISRAM_T: 1542 case ERROR_MEM_ALLOC_SDRAM_T: 1543 case ERROR_BUF_MGR: 1544 case ERROR_MB_GROUP_ASSGN_T: 1545 case ERROR_FRAME_LIMIT_OVER: 1546 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT: 1547 case ERROR_PROFILE_NOT_SUPPORTED: 1548 case ERROR_INIT_NOT_DONE: 1549 case IVD_MEM_ALLOC_FAILED: 1550 temp = 1 << IVD_FATALERROR; 1551 H264_DEC_DEBUG_PRINT("\nFatal Error\n"); 1552 break; 1553 1554 case ERROR_DBP_MANAGER_T: 1555 case ERROR_GAPS_IN_FRM_NUM: 1556 case ERROR_UNKNOWN_NAL: 1557 case ERROR_INV_MB_SLC_GRP_T: 1558 case ERROR_MULTIPLE_SLC_GRP_T: 1559 case ERROR_UNKNOWN_LEVEL: 1560 case ERROR_UNAVAIL_PICBUF_T: 1561 case ERROR_UNAVAIL_MVBUF_T: 1562 case ERROR_UNAVAIL_DISPBUF_T: 1563 case ERROR_NUM_REF: 1564 case ERROR_REFIDX_ORDER_T: 1565 case ERROR_PIC0_NOT_FOUND_T: 1566 case ERROR_MB_TYPE: 1567 case ERROR_SUB_MB_TYPE: 1568 case ERROR_CBP: 1569 case ERROR_REF_IDX: 1570 case ERROR_NUM_MV: 1571 case ERROR_CHROMA_PRED_MODE: 1572 case ERROR_INTRAPRED: 1573 case ERROR_NEXT_MB_ADDRESS_T: 1574 case ERROR_MB_ADDRESS_T: 1575 case ERROR_PIC1_NOT_FOUND_T: 1576 case ERROR_CAVLC_NUM_COEFF_T: 1577 case ERROR_CAVLC_SCAN_POS_T: 1578 case ERROR_PRED_WEIGHT_TABLE_T: 1579 case ERROR_CORRUPTED_SLICE: 1580 temp = 1 << IVD_CORRUPTEDDATA; 1581 break; 1582 1583 case ERROR_NOT_SUPP_RESOLUTION: 1584 case ERROR_FEATURE_UNAVAIL: 1585 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT: 1586 temp = 1 << IVD_UNSUPPORTEDINPUT; 1587 break; 1588 1589 case ERROR_INVALID_PIC_PARAM: 1590 case ERROR_INVALID_SEQ_PARAM: 1591 case ERROR_EGC_EXCEED_32_1_T: 1592 case ERROR_EGC_EXCEED_32_2_T: 1593 case ERROR_INV_RANGE_TEV_T: 1594 case ERROR_INV_SLC_TYPE_T: 1595 case ERROR_INV_POC_TYPE_T: 1596 case ERROR_INV_RANGE_QP_T: 1597 case ERROR_INV_SPS_PPS_T: 1598 case ERROR_INV_SLICE_HDR_T: 1599 temp = 1 << IVD_CORRUPTEDHEADER; 1600 break; 1601 1602 case ERROR_EOB_FLUSHBITS_T: 1603 case ERROR_EOB_GETBITS_T: 1604 case ERROR_EOB_GETBIT_T: 1605 case ERROR_EOB_BYPASS_T: 1606 case ERROR_EOB_DECISION_T: 1607 case ERROR_EOB_TERMINATE_T: 1608 case ERROR_EOB_READCOEFF4X4CAB_T: 1609 temp = 1 << IVD_INSUFFICIENTDATA; 1610 break; 1611 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED: 1612 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH: 1613 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR; 1614 break; 1615 1616 case ERROR_DANGLING_FIELD_IN_PIC: 1617 temp = 1 << IVD_APPLIEDCONCEALMENT; 1618 break; 1619 1620 } 1621 1622 return temp; 1623 1624 } 1625 1626 UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd, 1627 UWORD32 pic_ht, 1628 UWORD8 u1_chroma_format, 1629 UWORD32 *p_buf_size) 1630 { 1631 UWORD32 u4_min_num_out_bufs = 0; 1632 1633 if(u1_chroma_format == IV_YUV_420P) 1634 u4_min_num_out_bufs = MIN_OUT_BUFS_420; 1635 else if(u1_chroma_format == IV_YUV_422ILE) 1636 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 1637 else if(u1_chroma_format == IV_RGB_565) 1638 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 1639 else if((u1_chroma_format == IV_YUV_420SP_UV) 1640 || (u1_chroma_format == IV_YUV_420SP_VU)) 1641 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 1642 1643 if(u1_chroma_format == IV_YUV_420P) 1644 { 1645 p_buf_size[0] = (pic_wd * pic_ht); 1646 p_buf_size[1] = (pic_wd * pic_ht) >> 2; 1647 p_buf_size[2] = (pic_wd * pic_ht) >> 2; 1648 } 1649 else if(u1_chroma_format == IV_YUV_422ILE) 1650 { 1651 p_buf_size[0] = (pic_wd * pic_ht) * 2; 1652 p_buf_size[1] = p_buf_size[2] = 0; 1653 } 1654 else if(u1_chroma_format == IV_RGB_565) 1655 { 1656 p_buf_size[0] = (pic_wd * pic_ht) * 2; 1657 p_buf_size[1] = p_buf_size[2] = 0; 1658 } 1659 else if((u1_chroma_format == IV_YUV_420SP_UV) 1660 || (u1_chroma_format == IV_YUV_420SP_VU)) 1661 { 1662 p_buf_size[0] = (pic_wd * pic_ht); 1663 p_buf_size[1] = (pic_wd * pic_ht) >> 1; 1664 p_buf_size[2] = 0; 1665 } 1666 1667 return u4_min_num_out_bufs; 1668 } 1669 1670 WORD32 check_app_out_buf_size(dec_struct_t *ps_dec) 1671 { 1672 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS]; 1673 UWORD32 u4_min_num_out_bufs, i; 1674 UWORD32 pic_wd, pic_ht; 1675 1676 if(0 == ps_dec->u4_share_disp_buf) 1677 { 1678 pic_wd = ps_dec->u2_disp_width; 1679 pic_ht = ps_dec->u2_disp_height; 1680 1681 } 1682 else 1683 { 1684 /* In case of shared mode, do not check validity of ps_dec->ps_out_buffer */ 1685 return (IV_SUCCESS); 1686 } 1687 1688 if(ps_dec->u4_app_disp_width > pic_wd) 1689 pic_wd = ps_dec->u4_app_disp_width; 1690 1691 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht, 1692 ps_dec->u1_chroma_format, 1693 &au4_min_out_buf_size[0]); 1694 1695 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs) 1696 return IV_FAIL; 1697 1698 for(i = 0; i < u4_min_num_out_bufs; i++) 1699 { 1700 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] 1701 < au4_min_out_buf_size[i]) 1702 return (IV_FAIL); 1703 } 1704 1705 return (IV_SUCCESS); 1706 } 1707 1708 1709 /*****************************************************************************/ 1710 /* */ 1711 /* Function Name : ih264d_video_decode */ 1712 /* */ 1713 /* Description : handle video decode API command */ 1714 /* */ 1715 /* Inputs :iv_obj_t decoder handle */ 1716 /* :pv_api_ip pointer to input structure */ 1717 /* :pv_api_op pointer to output structure */ 1718 /* Outputs : */ 1719 /* Returns : void */ 1720 /* */ 1721 /* Issues : none */ 1722 /* */ 1723 /* Revision History: */ 1724 /* */ 1725 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1726 /* 22 10 2008 100356 Draft */ 1727 /* */ 1728 /*****************************************************************************/ 1729 1730 WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1731 { 1732 /* ! */ 1733 1734 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 1735 1736 WORD32 i4_err_status = 0; 1737 UWORD8 *pu1_buf = NULL; 1738 WORD32 buflen; 1739 UWORD32 u4_max_ofst, u4_length_of_start_code = 0; 1740 1741 UWORD32 bytes_consumed = 0; 1742 UWORD32 cur_slice_is_nonref = 0; 1743 UWORD32 u4_next_is_aud; 1744 UWORD32 u4_first_start_code_found = 0; 1745 WORD32 ret = 0,api_ret_value = IV_SUCCESS; 1746 WORD32 header_data_left = 0,frame_data_left = 0; 1747 UWORD8 *pu1_bitstrm_buf; 1748 ivd_video_decode_ip_t *ps_dec_ip; 1749 ivd_video_decode_op_t *ps_dec_op; 1750 1751 ithread_set_name((void*)"Parse_thread"); 1752 1753 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip; 1754 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op; 1755 1756 { 1757 UWORD32 u4_size; 1758 u4_size = ps_dec_op->u4_size; 1759 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t)); 1760 ps_dec_op->u4_size = u4_size; 1761 } 1762 1763 ps_dec->pv_dec_out = ps_dec_op; 1764 if(ps_dec->init_done != 1) 1765 { 1766 return IV_FAIL; 1767 } 1768 1769 /*Data memory barries instruction,so that bitstream write by the application is complete*/ 1770 DATA_SYNC(); 1771 1772 if(0 == ps_dec->u1_flushfrm) 1773 { 1774 if(ps_dec_ip->pv_stream_buffer == NULL) 1775 { 1776 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1777 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 1778 return IV_FAIL; 1779 } 1780 if(ps_dec_ip->u4_num_Bytes <= 0) 1781 { 1782 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1783 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV; 1784 return IV_FAIL; 1785 1786 } 1787 } 1788 ps_dec->u1_pic_decode_done = 0; 1789 1790 ps_dec_op->u4_num_bytes_consumed = 0; 1791 1792 ps_dec->ps_out_buffer = NULL; 1793 1794 if(ps_dec_ip->u4_size 1795 >= offsetof(ivd_video_decode_ip_t, s_out_buffer)) 1796 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer; 1797 1798 ps_dec->u4_fmt_conv_cur_row = 0; 1799 1800 ps_dec->u4_output_present = 0; 1801 ps_dec->s_disp_op.u4_error_code = 1; 1802 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS; 1803 if(0 == ps_dec->u4_share_disp_buf 1804 && ps_dec->i4_decode_header == 0) 1805 { 1806 UWORD32 i; 1807 if(ps_dec->ps_out_buffer->u4_num_bufs == 0) 1808 { 1809 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1810 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 1811 return IV_FAIL; 1812 } 1813 1814 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++) 1815 { 1816 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL) 1817 { 1818 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1819 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 1820 return IV_FAIL; 1821 } 1822 1823 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0) 1824 { 1825 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1826 ps_dec_op->u4_error_code |= 1827 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 1828 return IV_FAIL; 1829 } 1830 } 1831 } 1832 1833 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT) 1834 { 1835 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER; 1836 return IV_FAIL; 1837 } 1838 1839 /* ! */ 1840 ps_dec->u4_ts = ps_dec_ip->u4_ts; 1841 1842 ps_dec_op->u4_error_code = 0; 1843 ps_dec_op->e_pic_type = -1; 1844 ps_dec_op->u4_output_present = 0; 1845 ps_dec_op->u4_frame_decoded_flag = 0; 1846 1847 ps_dec->i4_frametype = -1; 1848 ps_dec->i4_content_type = -1; 1849 1850 ps_dec->u4_slice_start_code_found = 0; 1851 1852 /* In case the deocder is not in flush mode(in shared mode), 1853 then decoder has to pick up a buffer to write current frame. 1854 Check if a frame is available in such cases */ 1855 1856 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1 1857 && ps_dec->u1_flushfrm == 0) 1858 { 1859 UWORD32 i; 1860 1861 WORD32 disp_avail = 0, free_id; 1862 1863 /* Check if at least one buffer is available with the codec */ 1864 /* If not then return to application with error */ 1865 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1866 { 1867 if(0 == ps_dec->u4_disp_buf_mapping[i] 1868 || 1 == ps_dec->u4_disp_buf_to_be_freed[i]) 1869 { 1870 disp_avail = 1; 1871 break; 1872 } 1873 1874 } 1875 1876 if(0 == disp_avail) 1877 { 1878 /* If something is queued for display wait for that buffer to be returned */ 1879 1880 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1881 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 1882 return (IV_FAIL); 1883 } 1884 1885 while(1) 1886 { 1887 pic_buffer_t *ps_pic_buf; 1888 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free( 1889 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id); 1890 1891 if(ps_pic_buf == NULL) 1892 { 1893 UWORD32 i, display_queued = 0; 1894 1895 /* check if any buffer was given for display which is not returned yet */ 1896 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1897 { 1898 if(0 != ps_dec->u4_disp_buf_mapping[i]) 1899 { 1900 display_queued = 1; 1901 break; 1902 } 1903 } 1904 /* If some buffer is queued for display, then codec has to singal an error and wait 1905 for that buffer to be returned. 1906 If nothing is queued for display then codec has ownership of all display buffers 1907 and it can reuse any of the existing buffers and continue decoding */ 1908 1909 if(1 == display_queued) 1910 { 1911 /* If something is queued for display wait for that buffer to be returned */ 1912 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1913 ps_dec_op->u4_error_code |= (1 1914 << IVD_UNSUPPORTEDPARAM); 1915 return (IV_FAIL); 1916 } 1917 } 1918 else 1919 { 1920 /* If the buffer is with display, then mark it as in use and then look for a buffer again */ 1921 if(1 == ps_dec->u4_disp_buf_mapping[free_id]) 1922 { 1923 ih264_buf_mgr_set_status( 1924 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1925 free_id, 1926 BUF_MGR_IO); 1927 } 1928 else 1929 { 1930 /** 1931 * Found a free buffer for present call. Release it now. 1932 * Will be again obtained later. 1933 */ 1934 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1935 free_id, 1936 BUF_MGR_IO); 1937 break; 1938 } 1939 } 1940 } 1941 1942 } 1943 1944 if(ps_dec->u1_flushfrm) 1945 { 1946 if(ps_dec->u1_init_dec_flag == 0) 1947 { 1948 /*Come out of flush mode and return*/ 1949 ps_dec->u1_flushfrm = 0; 1950 return (IV_FAIL); 1951 } 1952 1953 1954 1955 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 1956 &(ps_dec->s_disp_op)); 1957 if(0 == ps_dec->s_disp_op.u4_error_code) 1958 { 1959 /* check output buffer size given by the application */ 1960 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS) 1961 { 1962 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 1963 return (IV_FAIL); 1964 } 1965 1966 ps_dec->u4_fmt_conv_cur_row = 0; 1967 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht; 1968 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 1969 ps_dec->u4_fmt_conv_cur_row, 1970 ps_dec->u4_fmt_conv_num_rows); 1971 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 1972 ps_dec->u4_output_present = 1; 1973 1974 } 1975 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 1976 1977 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 1978 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 1979 1980 ps_dec_op->u4_new_seq = 0; 1981 1982 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 1983 ps_dec_op->u4_progressive_frame_flag = 1984 ps_dec->s_disp_op.u4_progressive_frame_flag; 1985 ps_dec_op->e_output_format = 1986 ps_dec->s_disp_op.e_output_format; 1987 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 1988 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 1989 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 1990 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 1991 1992 /*In the case of flush ,since no frame is decoded set pic type as invalid*/ 1993 ps_dec_op->u4_is_ref_flag = -1; 1994 ps_dec_op->e_pic_type = IV_NA_FRAME; 1995 ps_dec_op->u4_frame_decoded_flag = 0; 1996 1997 if(0 == ps_dec->s_disp_op.u4_error_code) 1998 { 1999 return (IV_SUCCESS); 2000 } 2001 else 2002 return (IV_FAIL); 2003 2004 } 2005 if(ps_dec->u1_res_changed == 1) 2006 { 2007 /*if resolution has changed and all buffers have been flushed, reset decoder*/ 2008 ih264d_init_decoder(ps_dec); 2009 } 2010 2011 ps_dec->u4_prev_nal_skipped = 0; 2012 2013 ps_dec->u2_cur_mb_addr = 0; 2014 ps_dec->u2_total_mbs_coded = 0; 2015 ps_dec->u2_cur_slice_num = 0; 2016 ps_dec->cur_dec_mb_num = 0; 2017 ps_dec->cur_recon_mb_num = 0; 2018 ps_dec->u4_first_slice_in_pic = 1; 2019 ps_dec->u1_slice_header_done = 0; 2020 ps_dec->u1_dangling_field = 0; 2021 2022 ps_dec->u4_dec_thread_created = 0; 2023 ps_dec->u4_bs_deblk_thread_created = 0; 2024 ps_dec->u4_cur_bs_mb_num = 0; 2025 ps_dec->u4_start_recon_deblk = 0; 2026 ps_dec->u4_sps_cnt_in_process = 0; 2027 2028 DEBUG_THREADS_PRINTF(" Starting process call\n"); 2029 2030 2031 ps_dec->u4_pic_buf_got = 0; 2032 2033 do 2034 { 2035 WORD32 buf_size; 2036 2037 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer 2038 + ps_dec_op->u4_num_bytes_consumed; 2039 2040 u4_max_ofst = ps_dec_ip->u4_num_Bytes 2041 - ps_dec_op->u4_num_bytes_consumed; 2042 2043 /* If dynamic bitstream buffer is not allocated and 2044 * header decode is done, then allocate dynamic bitstream buffer 2045 */ 2046 if((NULL == ps_dec->pu1_bits_buf_dynamic) && 2047 (ps_dec->i4_header_decoded & 1)) 2048 { 2049 WORD32 size; 2050 2051 void *pv_buf; 2052 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 2053 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2); 2054 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2055 RETURN_IF((NULL == pv_buf), IV_FAIL); 2056 ps_dec->pu1_bits_buf_dynamic = pv_buf; 2057 ps_dec->u4_dynamic_bits_buf_size = size; 2058 } 2059 2060 if(ps_dec->pu1_bits_buf_dynamic) 2061 { 2062 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic; 2063 buf_size = ps_dec->u4_dynamic_bits_buf_size; 2064 } 2065 else 2066 { 2067 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static; 2068 buf_size = ps_dec->u4_static_bits_buf_size; 2069 } 2070 2071 u4_next_is_aud = 0; 2072 2073 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst, 2074 &u4_length_of_start_code, 2075 &u4_next_is_aud); 2076 2077 if(buflen == -1) 2078 buflen = 0; 2079 /* Ignore bytes beyond the allocated size of intermediate buffer */ 2080 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the 2081 end of the buffer, which will be memset to 0 after emulation prevention */ 2082 buflen = MIN(buflen, buf_size - 8); 2083 2084 bytes_consumed = buflen + u4_length_of_start_code; 2085 ps_dec_op->u4_num_bytes_consumed += bytes_consumed; 2086 2087 { 2088 UWORD8 u1_firstbyte, u1_nal_ref_idc; 2089 2090 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B) 2091 { 2092 u1_firstbyte = *(pu1_buf + u4_length_of_start_code); 2093 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte)); 2094 if(u1_nal_ref_idc == 0) 2095 { 2096 /*skip non reference frames*/ 2097 cur_slice_is_nonref = 1; 2098 continue; 2099 } 2100 else 2101 { 2102 if(1 == cur_slice_is_nonref) 2103 { 2104 /*We have encountered a referenced frame,return to app*/ 2105 ps_dec_op->u4_num_bytes_consumed -= 2106 bytes_consumed; 2107 ps_dec_op->e_pic_type = IV_B_FRAME; 2108 ps_dec_op->u4_error_code = 2109 IVD_DEC_FRM_SKIPPED; 2110 ps_dec_op->u4_error_code |= (1 2111 << IVD_UNSUPPORTEDPARAM); 2112 ps_dec_op->u4_frame_decoded_flag = 0; 2113 ps_dec_op->u4_size = 2114 sizeof(ivd_video_decode_op_t); 2115 /*signal the decode thread*/ 2116 ih264d_signal_decode_thread(ps_dec); 2117 /* close deblock thread if it is not closed yet*/ 2118 if(ps_dec->u4_num_cores == 3) 2119 { 2120 ih264d_signal_bs_deblk_thread(ps_dec); 2121 } 2122 2123 return (IV_FAIL); 2124 } 2125 } 2126 2127 } 2128 2129 } 2130 2131 2132 if(buflen) 2133 { 2134 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code, 2135 buflen); 2136 /* Decoder may read extra 8 bytes near end of the frame */ 2137 if((buflen + 8) < buf_size) 2138 { 2139 memset(pu1_bitstrm_buf + buflen, 0, 8); 2140 } 2141 u4_first_start_code_found = 1; 2142 2143 } 2144 else 2145 { 2146 /*start code not found*/ 2147 2148 if(u4_first_start_code_found == 0) 2149 { 2150 /*no start codes found in current process call*/ 2151 2152 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND; 2153 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA; 2154 2155 if(ps_dec->u4_pic_buf_got == 0) 2156 { 2157 2158 ih264d_fill_output_struct_from_context(ps_dec, 2159 ps_dec_op); 2160 2161 ps_dec_op->u4_error_code = ps_dec->i4_error_code; 2162 ps_dec_op->u4_frame_decoded_flag = 0; 2163 2164 return (IV_FAIL); 2165 } 2166 else 2167 { 2168 ps_dec->u1_pic_decode_done = 1; 2169 continue; 2170 } 2171 } 2172 else 2173 { 2174 /* a start code has already been found earlier in the same process call*/ 2175 frame_data_left = 0; 2176 header_data_left = 0; 2177 continue; 2178 } 2179 2180 } 2181 2182 ps_dec->u4_return_to_app = 0; 2183 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op, 2184 pu1_bitstrm_buf, buflen); 2185 if(ret != OK) 2186 { 2187 UWORD32 error = ih264d_map_error(ret); 2188 ps_dec_op->u4_error_code = error | ret; 2189 api_ret_value = IV_FAIL; 2190 2191 if((ret == IVD_RES_CHANGED) 2192 || (ret == IVD_MEM_ALLOC_FAILED) 2193 || (ret == ERROR_UNAVAIL_PICBUF_T) 2194 || (ret == ERROR_UNAVAIL_MVBUF_T) 2195 || (ret == ERROR_INV_SPS_PPS_T) 2196 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE)) 2197 { 2198 ps_dec->u4_slice_start_code_found = 0; 2199 break; 2200 } 2201 2202 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC)) 2203 { 2204 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2205 api_ret_value = IV_FAIL; 2206 break; 2207 } 2208 2209 if(ret == ERROR_IN_LAST_SLICE_OF_PIC) 2210 { 2211 api_ret_value = IV_FAIL; 2212 break; 2213 } 2214 2215 } 2216 2217 if(ps_dec->u4_return_to_app) 2218 { 2219 /*We have encountered a referenced frame,return to app*/ 2220 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2221 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2222 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2223 ps_dec_op->u4_frame_decoded_flag = 0; 2224 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2225 /*signal the decode thread*/ 2226 ih264d_signal_decode_thread(ps_dec); 2227 /* close deblock thread if it is not closed yet*/ 2228 if(ps_dec->u4_num_cores == 3) 2229 { 2230 ih264d_signal_bs_deblk_thread(ps_dec); 2231 } 2232 return (IV_FAIL); 2233 2234 } 2235 2236 2237 2238 header_data_left = ((ps_dec->i4_decode_header == 1) 2239 && (ps_dec->i4_header_decoded != 3) 2240 && (ps_dec_op->u4_num_bytes_consumed 2241 < ps_dec_ip->u4_num_Bytes)); 2242 frame_data_left = (((ps_dec->i4_decode_header == 0) 2243 && ((ps_dec->u1_pic_decode_done == 0) 2244 || (u4_next_is_aud == 1))) 2245 && (ps_dec_op->u4_num_bytes_consumed 2246 < ps_dec_ip->u4_num_Bytes)); 2247 } 2248 while(( header_data_left == 1)||(frame_data_left == 1)); 2249 2250 if((ps_dec->u4_slice_start_code_found == 1) 2251 && (ret != IVD_MEM_ALLOC_FAILED) 2252 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2253 { 2254 // last slice - missing/corruption 2255 WORD32 num_mb_skipped; 2256 WORD32 prev_slice_err; 2257 pocstruct_t temp_poc; 2258 WORD32 ret1; 2259 WORD32 ht_in_mbs; 2260 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag); 2261 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2262 - ps_dec->u2_total_mbs_coded; 2263 2264 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0)) 2265 prev_slice_err = 1; 2266 else 2267 prev_slice_err = 2; 2268 2269 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0)) 2270 prev_slice_err = 1; 2271 2272 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num, 2273 &temp_poc, prev_slice_err); 2274 2275 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) || 2276 (ret1 == ERROR_INV_SPS_PPS_T)) 2277 { 2278 ret = ret1; 2279 } 2280 } 2281 2282 if((ret == IVD_RES_CHANGED) 2283 || (ret == IVD_MEM_ALLOC_FAILED) 2284 || (ret == ERROR_UNAVAIL_PICBUF_T) 2285 || (ret == ERROR_UNAVAIL_MVBUF_T) 2286 || (ret == ERROR_INV_SPS_PPS_T)) 2287 { 2288 2289 /* signal the decode thread */ 2290 ih264d_signal_decode_thread(ps_dec); 2291 /* close deblock thread if it is not closed yet */ 2292 if(ps_dec->u4_num_cores == 3) 2293 { 2294 ih264d_signal_bs_deblk_thread(ps_dec); 2295 } 2296 /* dont consume bitstream for change in resolution case */ 2297 if(ret == IVD_RES_CHANGED) 2298 { 2299 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2300 } 2301 return IV_FAIL; 2302 } 2303 2304 2305 if(ps_dec->u1_separate_parse) 2306 { 2307 /* If Format conversion is not complete, 2308 complete it here */ 2309 if(ps_dec->u4_num_cores == 2) 2310 { 2311 2312 /*do deblocking of all mbs*/ 2313 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0)) 2314 { 2315 UWORD32 u4_num_mbs,u4_max_addr; 2316 tfr_ctxt_t s_tfr_ctxt; 2317 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; 2318 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr; 2319 2320 /*BS is done for all mbs while parsing*/ 2321 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1; 2322 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1; 2323 2324 2325 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 2326 ps_dec->u2_frm_wd_in_mbs, 0); 2327 2328 2329 u4_num_mbs = u4_max_addr 2330 - ps_dec->u4_cur_deblk_mb_num + 1; 2331 2332 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs); 2333 2334 if(u4_num_mbs != 0) 2335 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, 2336 ps_tfr_cxt,1); 2337 2338 ps_dec->u4_start_recon_deblk = 0; 2339 2340 } 2341 2342 } 2343 2344 /*signal the decode thread*/ 2345 ih264d_signal_decode_thread(ps_dec); 2346 /* close deblock thread if it is not closed yet*/ 2347 if(ps_dec->u4_num_cores == 3) 2348 { 2349 ih264d_signal_bs_deblk_thread(ps_dec); 2350 } 2351 } 2352 2353 2354 DATA_SYNC(); 2355 2356 2357 if((ps_dec_op->u4_error_code & 0xff) 2358 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 2359 { 2360 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2361 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2362 } 2363 2364 //Report if header (sps and pps) has not been decoded yet 2365 if(ps_dec->i4_header_decoded != 3) 2366 { 2367 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2368 2369 } 2370 2371 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3) 2372 { 2373 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2374 2375 } 2376 if(ps_dec->u4_prev_nal_skipped) 2377 { 2378 /*We have encountered a referenced frame,return to app*/ 2379 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2380 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2381 ps_dec_op->u4_frame_decoded_flag = 0; 2382 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2383 /* close deblock thread if it is not closed yet*/ 2384 if(ps_dec->u4_num_cores == 3) 2385 { 2386 ih264d_signal_bs_deblk_thread(ps_dec); 2387 } 2388 return (IV_FAIL); 2389 2390 } 2391 2392 if((ps_dec->u4_slice_start_code_found == 1) 2393 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status)) 2394 { 2395 /* 2396 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 2397 */ 2398 2399 if(ps_dec->ps_cur_slice->u1_field_pic_flag) 2400 { 2401 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag) 2402 { 2403 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY; 2404 } 2405 else 2406 { 2407 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY; 2408 } 2409 } 2410 else 2411 { 2412 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY; 2413 } 2414 2415 /* if new frame in not found (if we are still getting slices from previous frame) 2416 * ih264d_deblock_display is not called. Such frames will not be added to reference /display 2417 */ 2418 if (((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) 2419 && (ps_dec->u4_pic_buf_got == 1)) 2420 { 2421 /* Calling Function to deblock Picture and Display */ 2422 ret = ih264d_deblock_display(ps_dec); 2423 } 2424 2425 2426 /*set to complete ,as we dont support partial frame decode*/ 2427 if(ps_dec->i4_header_decoded == 3) 2428 { 2429 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 2430 } 2431 2432 /*Update the i4_frametype at the end of picture*/ 2433 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 2434 { 2435 ps_dec->i4_frametype = IV_IDR_FRAME; 2436 } 2437 else if(ps_dec->i4_pic_type == B_SLICE) 2438 { 2439 ps_dec->i4_frametype = IV_B_FRAME; 2440 } 2441 else if(ps_dec->i4_pic_type == P_SLICE) 2442 { 2443 ps_dec->i4_frametype = IV_P_FRAME; 2444 } 2445 else if(ps_dec->i4_pic_type == I_SLICE) 2446 { 2447 ps_dec->i4_frametype = IV_I_FRAME; 2448 } 2449 else 2450 { 2451 H264_DEC_DEBUG_PRINT("Shouldn't come here\n"); 2452 } 2453 2454 //Update the content type 2455 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag; 2456 2457 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2; 2458 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded 2459 - ps_dec->ps_cur_slice->u1_field_pic_flag; 2460 2461 } 2462 2463 /* close deblock thread if it is not closed yet*/ 2464 if(ps_dec->u4_num_cores == 3) 2465 { 2466 ih264d_signal_bs_deblk_thread(ps_dec); 2467 } 2468 2469 2470 { 2471 /* In case the decoder is configured to run in low delay mode, 2472 * then get display buffer and then format convert. 2473 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles 2474 */ 2475 2476 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode) 2477 && ps_dec->u1_init_dec_flag) 2478 { 2479 2480 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 2481 &(ps_dec->s_disp_op)); 2482 if(0 == ps_dec->s_disp_op.u4_error_code) 2483 { 2484 ps_dec->u4_fmt_conv_cur_row = 0; 2485 ps_dec->u4_output_present = 1; 2486 } 2487 } 2488 2489 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 2490 2491 /* If Format conversion is not complete, 2492 complete it here */ 2493 if(ps_dec->u4_output_present && 2494 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 2495 { 2496 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht 2497 - ps_dec->u4_fmt_conv_cur_row; 2498 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2499 ps_dec->u4_fmt_conv_cur_row, 2500 ps_dec->u4_fmt_conv_num_rows); 2501 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2502 } 2503 2504 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2505 } 2506 2507 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1) 2508 { 2509 ps_dec_op->u4_progressive_frame_flag = 1; 2510 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2511 { 2512 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag) 2513 && (0 == ps_dec->ps_sps->u1_mb_aff_flag)) 2514 ps_dec_op->u4_progressive_frame_flag = 0; 2515 2516 } 2517 } 2518 2519 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded) 2520 { 2521 ps_dec->u1_top_bottom_decoded = 0; 2522 } 2523 /*--------------------------------------------------------------------*/ 2524 /* Do End of Pic processing. */ 2525 /* Should be called only if frame was decoded in previous process call*/ 2526 /*--------------------------------------------------------------------*/ 2527 if(ps_dec->u4_pic_buf_got == 1) 2528 { 2529 if(1 == ps_dec->u1_last_pic_not_decoded) 2530 { 2531 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec); 2532 2533 if(ret != OK) 2534 return ret; 2535 2536 ret = ih264d_end_of_pic(ps_dec); 2537 if(ret != OK) 2538 return ret; 2539 } 2540 else 2541 { 2542 ret = ih264d_end_of_pic(ps_dec); 2543 if(ret != OK) 2544 return ret; 2545 } 2546 2547 } 2548 2549 2550 /*Data memory barrier instruction,so that yuv write by the library is complete*/ 2551 DATA_SYNC(); 2552 2553 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n", 2554 ps_dec_op->u4_num_bytes_consumed); 2555 return api_ret_value; 2556 } 2557 2558 WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2559 { 2560 char version_string[MAXVERSION_STRLEN + 1]; 2561 UWORD32 version_string_len; 2562 2563 ivd_ctl_getversioninfo_ip_t *ps_ip; 2564 ivd_ctl_getversioninfo_op_t *ps_op; 2565 2566 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip; 2567 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op; 2568 UNUSED(dec_hdl); 2569 ps_op->u4_error_code = IV_SUCCESS; 2570 2571 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 2572 CODEC_VENDOR); 2573 2574 if((WORD32)ps_ip->u4_version_buffer_size <= 0) 2575 { 2576 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2577 return (IV_FAIL); 2578 } 2579 2580 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1; 2581 2582 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string))) 2583 { 2584 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len); 2585 ps_op->u4_error_code = IV_SUCCESS; 2586 } 2587 else 2588 { 2589 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2590 return IV_FAIL; 2591 } 2592 return (IV_SUCCESS); 2593 } 2594 2595 /*****************************************************************************/ 2596 /* */ 2597 /* Function Name : ih264d_get_display_frame */ 2598 /* */ 2599 /* Description : */ 2600 /* Inputs :iv_obj_t decoder handle */ 2601 /* :pv_api_ip pointer to input structure */ 2602 /* :pv_api_op pointer to output structure */ 2603 /* Outputs : */ 2604 /* Returns : void */ 2605 /* */ 2606 /* Issues : none */ 2607 /* */ 2608 /* Revision History: */ 2609 /* */ 2610 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2611 /* 22 10 2008 100356 Draft */ 2612 /* */ 2613 /*****************************************************************************/ 2614 WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl, 2615 void *pv_api_ip, 2616 void *pv_api_op) 2617 { 2618 2619 UNUSED(dec_hdl); 2620 UNUSED(pv_api_ip); 2621 UNUSED(pv_api_op); 2622 // This function is no longer needed, output is returned in the process() 2623 return IV_FAIL; 2624 } 2625 2626 /*****************************************************************************/ 2627 /* */ 2628 /* Function Name : ih264d_set_display_frame */ 2629 /* */ 2630 /* Description : */ 2631 /* */ 2632 /* Inputs :iv_obj_t decoder handle */ 2633 /* :pv_api_ip pointer to input structure */ 2634 /* :pv_api_op pointer to output structure */ 2635 /* Outputs : */ 2636 /* Returns : void */ 2637 /* */ 2638 /* Issues : none */ 2639 /* */ 2640 /* Revision History: */ 2641 /* */ 2642 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2643 /* 22 10 2008 100356 Draft */ 2644 /* */ 2645 /*****************************************************************************/ 2646 WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl, 2647 void *pv_api_ip, 2648 void *pv_api_op) 2649 { 2650 2651 ivd_set_display_frame_ip_t *dec_disp_ip; 2652 ivd_set_display_frame_op_t *dec_disp_op; 2653 2654 UWORD32 i; 2655 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2656 2657 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 2658 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 2659 dec_disp_op->u4_error_code = 0; 2660 2661 2662 ps_dec->u4_num_disp_bufs = 0; 2663 if(ps_dec->u4_share_disp_buf) 2664 { 2665 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs; 2666 2667 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW); 2668 2669 ps_dec->u4_num_disp_bufs = u4_num_bufs; 2670 for(i = 0; i < u4_num_bufs; i++) 2671 { 2672 ps_dec->disp_bufs[i].u4_num_bufs = 2673 dec_disp_ip->s_disp_buffer[i].u4_num_bufs; 2674 2675 ps_dec->disp_bufs[i].buf[0] = 2676 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 2677 ps_dec->disp_bufs[i].buf[1] = 2678 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 2679 ps_dec->disp_bufs[i].buf[2] = 2680 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 2681 2682 ps_dec->disp_bufs[i].u4_bufsize[0] = 2683 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]; 2684 ps_dec->disp_bufs[i].u4_bufsize[1] = 2685 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]; 2686 ps_dec->disp_bufs[i].u4_bufsize[2] = 2687 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]; 2688 2689 } 2690 } 2691 return IV_SUCCESS; 2692 2693 } 2694 2695 /*****************************************************************************/ 2696 /* */ 2697 /* Function Name : ih264d_set_flush_mode */ 2698 /* */ 2699 /* Description : */ 2700 /* */ 2701 /* Inputs :iv_obj_t decoder handle */ 2702 /* :pv_api_ip pointer to input structure */ 2703 /* :pv_api_op pointer to output structure */ 2704 /* Globals : <Does it use any global variables?> */ 2705 /* Outputs : */ 2706 /* Returns : void */ 2707 /* */ 2708 /* Issues : none */ 2709 /* */ 2710 /* Revision History: */ 2711 /* */ 2712 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2713 /* 22 10 2008 100356 Draft */ 2714 /* */ 2715 /*****************************************************************************/ 2716 WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2717 { 2718 dec_struct_t * ps_dec; 2719 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op; 2720 ps_ctl_op->u4_error_code = 0; 2721 2722 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2723 UNUSED(pv_api_ip); 2724 /* ! */ 2725 /* Signal flush frame control call */ 2726 ps_dec->u1_flushfrm = 1; 2727 2728 if(ps_dec->u1_init_dec_flag == 1) 2729 { 2730 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs); 2731 ih264d_release_display_bufs(ps_dec); 2732 } 2733 2734 ps_ctl_op->u4_error_code = 0; 2735 2736 /* Ignore dangling fields during flush */ 2737 ps_dec->u1_top_bottom_decoded = 0; 2738 2739 return IV_SUCCESS; 2740 } 2741 2742 /*****************************************************************************/ 2743 /* */ 2744 /* Function Name : ih264d_get_status */ 2745 /* */ 2746 /* Description : */ 2747 /* */ 2748 /* Inputs :iv_obj_t decoder handle */ 2749 /* :pv_api_ip pointer to input structure */ 2750 /* :pv_api_op pointer to output structure */ 2751 /* Globals : <Does it use any global variables?> */ 2752 /* Outputs : */ 2753 /* Returns : void */ 2754 /* */ 2755 /* Issues : none */ 2756 /* */ 2757 /* Revision History: */ 2758 /* */ 2759 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2760 /* 22 10 2008 100356 Draft */ 2761 /* */ 2762 /*****************************************************************************/ 2763 2764 WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2765 { 2766 2767 UWORD32 i; 2768 dec_struct_t * ps_dec; 2769 UWORD32 pic_wd, pic_ht; 2770 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op; 2771 UNUSED(pv_api_ip); 2772 ps_ctl_op->u4_error_code = 0; 2773 2774 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2775 2776 2777 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2778 { 2779 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height; 2780 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width; 2781 2782 if(0 == ps_dec->u4_share_disp_buf) 2783 { 2784 pic_wd = ps_dec->u2_disp_width; 2785 pic_ht = ps_dec->u2_disp_height; 2786 2787 } 2788 else 2789 { 2790 pic_wd = ps_dec->u2_frm_wd_y; 2791 pic_ht = ps_dec->u2_frm_ht_y; 2792 } 2793 } 2794 else 2795 { 2796 pic_wd = 0; 2797 pic_ht = 0; 2798 2799 ps_ctl_op->u4_pic_ht = pic_wd; 2800 ps_ctl_op->u4_pic_wd = pic_ht; 2801 2802 if(1 == ps_dec->u4_share_disp_buf) 2803 { 2804 pic_wd += (PAD_LEN_Y_H << 1); 2805 pic_ht += (PAD_LEN_Y_V << 2); 2806 2807 } 2808 2809 } 2810 2811 if(ps_dec->u4_app_disp_width > pic_wd) 2812 pic_wd = ps_dec->u4_app_disp_width; 2813 if(0 == ps_dec->u4_share_disp_buf) 2814 ps_ctl_op->u4_num_disp_bufs = 1; 2815 else 2816 { 2817 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2818 { 2819 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 2820 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 2821 { 2822 ps_ctl_op->u4_num_disp_bufs = 2823 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 2824 } 2825 else 2826 { 2827 /*if VUI is not present assume maximum possible refrence frames for the level, 2828 * as max reorder frames*/ 2829 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 2830 } 2831 2832 ps_ctl_op->u4_num_disp_bufs += 2833 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2834 } 2835 else 2836 { 2837 ps_ctl_op->u4_num_disp_bufs = 32; 2838 } 2839 ps_ctl_op->u4_num_disp_bufs = MAX( 2840 ps_ctl_op->u4_num_disp_bufs, 6); 2841 ps_ctl_op->u4_num_disp_bufs = MIN( 2842 ps_ctl_op->u4_num_disp_bufs, 32); 2843 } 2844 2845 ps_ctl_op->u4_error_code = ps_dec->i4_error_code; 2846 2847 ps_ctl_op->u4_frame_rate = 0; //make it proper 2848 ps_ctl_op->u4_bit_rate = 0; //make it proper 2849 ps_ctl_op->e_content_type = ps_dec->i4_content_type; 2850 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format; 2851 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 2852 2853 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2854 { 2855 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 2856 } 2857 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2858 { 2859 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 2860 } 2861 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2862 { 2863 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 2864 } 2865 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2866 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2867 { 2868 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 2869 } 2870 2871 else 2872 { 2873 //Invalid chroma format; Error code may be updated, verify in testing if needed 2874 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL; 2875 return IV_FAIL; 2876 } 2877 2878 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 2879 { 2880 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 2881 } 2882 2883 /*!*/ 2884 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2885 { 2886 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2887 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2888 >> 2; 2889 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 2890 >> 2; 2891 } 2892 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2893 { 2894 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2895 * 2; 2896 ps_ctl_op->u4_min_out_buf_size[1] = 2897 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2898 } 2899 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2900 { 2901 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2902 * 2; 2903 ps_ctl_op->u4_min_out_buf_size[1] = 2904 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2905 } 2906 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2907 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2908 { 2909 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2910 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2911 >> 1; 2912 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2913 } 2914 2915 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 2916 return IV_SUCCESS; 2917 } 2918 2919 /*****************************************************************************/ 2920 /* */ 2921 /* Function Name : ih264d_get_buf_info */ 2922 /* */ 2923 /* Description : */ 2924 /* */ 2925 /* Inputs :iv_obj_t decoder handle */ 2926 /* :pv_api_ip pointer to input structure */ 2927 /* :pv_api_op pointer to output structure */ 2928 /* Globals : <Does it use any global variables?> */ 2929 /* Outputs : */ 2930 /* Returns : void */ 2931 /* */ 2932 /* Issues : none */ 2933 /* */ 2934 /* Revision History: */ 2935 /* */ 2936 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2937 /* 22 10 2008 100356 Draft */ 2938 /* */ 2939 /*****************************************************************************/ 2940 WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2941 { 2942 2943 dec_struct_t * ps_dec; 2944 UWORD8 i = 0; // Default for 420P format 2945 UWORD16 pic_wd, pic_ht; 2946 ivd_ctl_getbufinfo_op_t *ps_ctl_op = 2947 (ivd_ctl_getbufinfo_op_t*)pv_api_op; 2948 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS]; 2949 UNUSED(pv_api_ip); 2950 2951 ps_ctl_op->u4_error_code = 0; 2952 2953 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2954 2955 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 2956 2957 2958 ps_ctl_op->u4_num_disp_bufs = 1; 2959 2960 2961 pic_wd = 0; 2962 pic_ht = 0; 2963 2964 if(ps_dec->i4_header_decoded == 3) 2965 { 2966 2967 if(0 == ps_dec->u4_share_disp_buf) 2968 { 2969 pic_wd = ps_dec->u2_disp_width; 2970 pic_ht = ps_dec->u2_disp_height; 2971 2972 } 2973 else 2974 { 2975 pic_wd = ps_dec->u2_frm_wd_y; 2976 pic_ht = ps_dec->u2_frm_ht_y; 2977 } 2978 2979 } 2980 2981 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 2982 { 2983 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 2984 } 2985 if((WORD32)ps_dec->u4_app_disp_width > pic_wd) 2986 pic_wd = ps_dec->u4_app_disp_width; 2987 2988 if(0 == ps_dec->u4_share_disp_buf) 2989 ps_ctl_op->u4_num_disp_bufs = 1; 2990 else 2991 { 2992 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2993 { 2994 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 2995 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 2996 { 2997 ps_ctl_op->u4_num_disp_bufs = 2998 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 2999 } 3000 else 3001 { 3002 /*if VUI is not present assume maximum possible refrence frames for the level, 3003 * as max reorder frames*/ 3004 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 3005 } 3006 3007 ps_ctl_op->u4_num_disp_bufs += 3008 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3009 3010 } 3011 else 3012 { 3013 ps_ctl_op->u4_num_disp_bufs = 32; 3014 3015 } 3016 3017 ps_ctl_op->u4_num_disp_bufs = MAX( 3018 ps_ctl_op->u4_num_disp_bufs, 6); 3019 ps_ctl_op->u4_num_disp_bufs = MIN( 3020 ps_ctl_op->u4_num_disp_bufs, 32); 3021 } 3022 3023 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size( 3024 pic_wd, pic_ht, ps_dec->u1_chroma_format, 3025 &au4_min_out_buf_size[0]); 3026 3027 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++) 3028 { 3029 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i]; 3030 } 3031 3032 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 3033 3034 return IV_SUCCESS; 3035 } 3036 3037 /*****************************************************************************/ 3038 /* */ 3039 /* Function Name : ih264d_set_params */ 3040 /* */ 3041 /* Description : */ 3042 /* */ 3043 /* Inputs :iv_obj_t decoder handle */ 3044 /* :pv_api_ip pointer to input structure */ 3045 /* :pv_api_op pointer to output structure */ 3046 /* Outputs : */ 3047 /* Returns : void */ 3048 /* */ 3049 /* Issues : none */ 3050 /* */ 3051 /* Revision History: */ 3052 /* */ 3053 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3054 /* 22 10 2008 100356 Draft */ 3055 /* */ 3056 /*****************************************************************************/ 3057 WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3058 { 3059 3060 dec_struct_t * ps_dec; 3061 WORD32 ret = IV_SUCCESS; 3062 3063 ivd_ctl_set_config_ip_t *ps_ctl_ip = 3064 (ivd_ctl_set_config_ip_t *)pv_api_ip; 3065 ivd_ctl_set_config_op_t *ps_ctl_op = 3066 (ivd_ctl_set_config_op_t *)pv_api_op; 3067 3068 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3069 3070 ps_dec->u4_skip_frm_mask = 0; 3071 3072 ps_ctl_op->u4_error_code = 0; 3073 3074 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode; 3075 3076 /*Is it really supported test it when you so the corner testing using test app*/ 3077 3078 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE) 3079 { 3080 3081 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P) 3082 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 3083 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B) 3084 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 3085 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB) 3086 { 3087 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 3088 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 3089 } 3090 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I) 3091 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT; 3092 else 3093 { 3094 //dynamic parameter not supported 3095 //Put an appropriate error code to return the error.. 3096 //when you do the error code tests and after that remove this comment 3097 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3098 ret = IV_FAIL; 3099 } 3100 } 3101 3102 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd) 3103 { 3104 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 3105 } 3106 else if(0 == ps_dec->i4_header_decoded) 3107 { 3108 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 3109 } 3110 else if(ps_ctl_ip->u4_disp_wd == 0) 3111 { 3112 ps_dec->u4_app_disp_width = 0; 3113 } 3114 else 3115 { 3116 /* 3117 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF) 3118 * does not propogate. 3119 */ 3120 ps_dec->u4_app_disp_width = 0; 3121 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3122 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 3123 ret = IV_FAIL; 3124 } 3125 3126 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME) 3127 ps_dec->i4_decode_header = 0; 3128 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER) 3129 ps_dec->i4_decode_header = 1; 3130 else 3131 { 3132 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3133 ps_dec->i4_decode_header = 1; 3134 ret = IV_FAIL; 3135 } 3136 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 3137 3138 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) && 3139 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT)) 3140 { 3141 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3142 ret = IV_FAIL; 3143 } 3144 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode; 3145 return ret; 3146 3147 } 3148 3149 /*****************************************************************************/ 3150 /* */ 3151 /* Function Name : ih264d_set_default_params */ 3152 /* */ 3153 /* Description : */ 3154 /* */ 3155 /* Inputs :iv_obj_t decoder handle */ 3156 /* :pv_api_ip pointer to input structure */ 3157 /* :pv_api_op pointer to output structure */ 3158 /* Outputs : */ 3159 /* Returns : void */ 3160 /* */ 3161 /* Issues : none */ 3162 /* */ 3163 /* Revision History: */ 3164 /* */ 3165 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3166 /* 08 08 2011 100421 Copied from set_params */ 3167 /* */ 3168 /*****************************************************************************/ 3169 WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl, 3170 void *pv_api_ip, 3171 void *pv_api_op) 3172 { 3173 3174 dec_struct_t * ps_dec; 3175 WORD32 ret = IV_SUCCESS; 3176 3177 ivd_ctl_set_config_op_t *ps_ctl_op = 3178 (ivd_ctl_set_config_op_t *)pv_api_op; 3179 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3180 UNUSED(pv_api_ip); 3181 3182 3183 { 3184 ps_dec->u4_app_disp_width = 0; 3185 ps_dec->u4_skip_frm_mask = 0; 3186 ps_dec->i4_decode_header = 1; 3187 3188 ps_ctl_op->u4_error_code = 0; 3189 } 3190 3191 3192 return ret; 3193 } 3194 /*****************************************************************************/ 3195 /* */ 3196 /* Function Name : ih264d_reset */ 3197 /* */ 3198 /* Description : */ 3199 /* */ 3200 /* Inputs :iv_obj_t decoder handle */ 3201 /* :pv_api_ip pointer to input structure */ 3202 /* :pv_api_op pointer to output structure */ 3203 /* Globals : <Does it use any global variables?> */ 3204 /* Outputs : */ 3205 /* Returns : void */ 3206 /* */ 3207 /* Issues : none */ 3208 /* */ 3209 /* Revision History: */ 3210 /* */ 3211 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3212 /* 22 10 2008 100356 Draft */ 3213 /* */ 3214 /*****************************************************************************/ 3215 WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3216 { 3217 dec_struct_t *ps_dec; 3218 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip; 3219 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op; 3220 3221 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3222 UNUSED(ps_ip); 3223 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 3224 ih264d_free_dynamic_bufs(ps_dec); 3225 ih264d_free_static_bufs(dec_hdl); 3226 return IV_SUCCESS; 3227 } 3228 /*****************************************************************************/ 3229 /* */ 3230 /* Function Name : ih264d_reset */ 3231 /* */ 3232 /* Description : */ 3233 /* */ 3234 /* Inputs :iv_obj_t decoder handle */ 3235 /* :pv_api_ip pointer to input structure */ 3236 /* :pv_api_op pointer to output structure */ 3237 /* Globals : <Does it use any global variables?> */ 3238 /* Outputs : */ 3239 /* Returns : void */ 3240 /* */ 3241 /* Issues : none */ 3242 /* */ 3243 /* Revision History: */ 3244 /* */ 3245 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3246 /* 22 10 2008 100356 Draft */ 3247 /* */ 3248 /*****************************************************************************/ 3249 WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3250 { 3251 dec_struct_t * ps_dec; 3252 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op; 3253 UNUSED(pv_api_ip); 3254 ps_ctl_op->u4_error_code = 0; 3255 3256 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3257 3258 if(ps_dec != NULL) 3259 { 3260 ih264d_init_decoder(ps_dec); 3261 } 3262 else 3263 { 3264 H264_DEC_DEBUG_PRINT( 3265 "\nReset called without Initializing the decoder\n"); 3266 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE; 3267 } 3268 3269 return IV_SUCCESS; 3270 } 3271 3272 /*****************************************************************************/ 3273 /* */ 3274 /* Function Name : ih264d_ctl */ 3275 /* */ 3276 /* Description : */ 3277 /* */ 3278 /* Inputs :iv_obj_t decoder handle */ 3279 /* :pv_api_ip pointer to input structure */ 3280 /* :pv_api_op pointer to output structure */ 3281 /* Outputs : */ 3282 /* Returns : void */ 3283 /* */ 3284 /* Issues : none */ 3285 /* */ 3286 /* Revision History: */ 3287 /* */ 3288 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3289 /* 22 10 2008 100356 Draft */ 3290 /* */ 3291 /*****************************************************************************/ 3292 WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3293 { 3294 ivd_ctl_set_config_ip_t *ps_ctl_ip; 3295 ivd_ctl_set_config_op_t *ps_ctl_op; 3296 WORD32 ret = IV_SUCCESS; 3297 UWORD32 subcommand; 3298 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3299 3300 if(ps_dec->init_done != 1) 3301 { 3302 //Return proper Error Code 3303 return IV_FAIL; 3304 } 3305 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip; 3306 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op; 3307 ps_ctl_op->u4_error_code = 0; 3308 subcommand = ps_ctl_ip->e_sub_cmd; 3309 3310 switch(subcommand) 3311 { 3312 case IVD_CMD_CTL_GETPARAMS: 3313 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip, 3314 (void *)pv_api_op); 3315 break; 3316 case IVD_CMD_CTL_SETPARAMS: 3317 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip, 3318 (void *)pv_api_op); 3319 break; 3320 case IVD_CMD_CTL_RESET: 3321 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op); 3322 break; 3323 case IVD_CMD_CTL_SETDEFAULT: 3324 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip, 3325 (void *)pv_api_op); 3326 break; 3327 case IVD_CMD_CTL_FLUSH: 3328 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip, 3329 (void *)pv_api_op); 3330 break; 3331 case IVD_CMD_CTL_GETBUFINFO: 3332 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip, 3333 (void *)pv_api_op); 3334 break; 3335 case IVD_CMD_CTL_GETVERSION: 3336 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip, 3337 (void *)pv_api_op); 3338 break; 3339 case IH264D_CMD_CTL_DEGRADE: 3340 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip, 3341 (void *)pv_api_op); 3342 break; 3343 3344 case IH264D_CMD_CTL_SET_NUM_CORES: 3345 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip, 3346 (void *)pv_api_op); 3347 break; 3348 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 3349 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip, 3350 (void *)pv_api_op); 3351 break; 3352 case IH264D_CMD_CTL_GET_VUI_PARAMS: 3353 ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip, 3354 (void *)pv_api_op); 3355 break; 3356 3357 case IH264D_CMD_CTL_SET_PROCESSOR: 3358 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip, 3359 (void *)pv_api_op); 3360 break; 3361 default: 3362 H264_DEC_DEBUG_PRINT("\ndo nothing\n") 3363 ; 3364 break; 3365 } 3366 3367 return ret; 3368 } 3369 /*****************************************************************************/ 3370 /* */ 3371 /* Function Name : ih264d_rel_display_frame */ 3372 /* */ 3373 /* Description : */ 3374 /* */ 3375 /* Inputs :iv_obj_t decoder handle */ 3376 /* :pv_api_ip pointer to input structure */ 3377 /* :pv_api_op pointer to output structure */ 3378 /* Outputs : */ 3379 /* Returns : void */ 3380 /* */ 3381 /* Issues : none */ 3382 /* */ 3383 /* Revision History: */ 3384 /* */ 3385 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3386 /* 22 10 2008 100356 Draft */ 3387 /* */ 3388 /*****************************************************************************/ 3389 WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl, 3390 void *pv_api_ip, 3391 void *pv_api_op) 3392 { 3393 3394 ivd_rel_display_frame_ip_t *ps_rel_ip; 3395 ivd_rel_display_frame_op_t *ps_rel_op; 3396 UWORD32 buf_released = 0; 3397 3398 UWORD32 u4_ts = -1; 3399 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3400 3401 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 3402 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op; 3403 ps_rel_op->u4_error_code = 0; 3404 u4_ts = ps_rel_ip->u4_disp_buf_id; 3405 3406 if(0 == ps_dec->u4_share_disp_buf) 3407 { 3408 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3409 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0; 3410 return IV_SUCCESS; 3411 } 3412 3413 if(ps_dec->pv_pic_buf_mgr != NULL) 3414 { 3415 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts]) 3416 { 3417 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 3418 ps_rel_ip->u4_disp_buf_id, 3419 BUF_MGR_IO); 3420 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3421 buf_released = 1; 3422 } 3423 } 3424 3425 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released)) 3426 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1; 3427 3428 return IV_SUCCESS; 3429 } 3430 3431 /** 3432 ******************************************************************************* 3433 * 3434 * @brief 3435 * Sets degrade params 3436 * 3437 * @par Description: 3438 * Sets degrade params. 3439 * Refer to ih264d_ctl_degrade_ip_t definition for details 3440 * 3441 * @param[in] ps_codec_obj 3442 * Pointer to codec object at API level 3443 * 3444 * @param[in] pv_api_ip 3445 * Pointer to input argument structure 3446 * 3447 * @param[out] pv_api_op 3448 * Pointer to output argument structure 3449 * 3450 * @returns Status 3451 * 3452 * @remarks 3453 * 3454 * 3455 ******************************************************************************* 3456 */ 3457 3458 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 3459 void *pv_api_ip, 3460 void *pv_api_op) 3461 { 3462 ih264d_ctl_degrade_ip_t *ps_ip; 3463 ih264d_ctl_degrade_op_t *ps_op; 3464 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle; 3465 3466 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 3467 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 3468 3469 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type; 3470 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval; 3471 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics; 3472 3473 ps_op->u4_error_code = 0; 3474 ps_codec->i4_degrade_pic_cnt = 0; 3475 3476 return IV_SUCCESS; 3477 } 3478 3479 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 3480 void *pv_api_ip, 3481 void *pv_api_op) 3482 { 3483 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 3484 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 3485 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3486 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 3487 3488 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 3489 3490 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 3491 UNUSED(ps_ip); 3492 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3493 { 3494 disp_wd = ps_dec->u2_disp_width; 3495 disp_ht = ps_dec->u2_disp_height; 3496 3497 if(0 == ps_dec->u4_share_disp_buf) 3498 { 3499 buffer_wd = disp_wd; 3500 buffer_ht = disp_ht; 3501 } 3502 else 3503 { 3504 buffer_wd = ps_dec->u2_frm_wd_y; 3505 buffer_ht = ps_dec->u2_frm_ht_y; 3506 } 3507 } 3508 else 3509 { 3510 disp_wd = 0; 3511 disp_ht = 0; 3512 3513 if(0 == ps_dec->u4_share_disp_buf) 3514 { 3515 buffer_wd = disp_wd; 3516 buffer_ht = disp_ht; 3517 } 3518 else 3519 { 3520 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1); 3521 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2); 3522 } 3523 } 3524 if(ps_dec->u4_app_disp_width > buffer_wd) 3525 buffer_wd = ps_dec->u4_app_disp_width; 3526 3527 if(0 == ps_dec->u4_share_disp_buf) 3528 { 3529 x_offset = 0; 3530 y_offset = 0; 3531 } 3532 else 3533 { 3534 y_offset = (PAD_LEN_Y_V << 1); 3535 x_offset = PAD_LEN_Y_H; 3536 3537 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid)) 3538 && (0 != ps_dec->u2_crop_offset_y)) 3539 { 3540 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y; 3541 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y; 3542 } 3543 } 3544 3545 ps_op->u4_disp_wd[0] = disp_wd; 3546 ps_op->u4_disp_ht[0] = disp_ht; 3547 ps_op->u4_buffer_wd[0] = buffer_wd; 3548 ps_op->u4_buffer_ht[0] = buffer_ht; 3549 ps_op->u4_x_offset[0] = x_offset; 3550 ps_op->u4_y_offset[0] = y_offset; 3551 3552 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 3553 >> 1); 3554 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 3555 >> 1); 3556 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 3557 >> 1); 3558 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 3559 >> 1); 3560 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = 3561 (ps_op->u4_x_offset[0] >> 1); 3562 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = 3563 (ps_op->u4_y_offset[0] >> 1); 3564 3565 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3566 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3567 { 3568 ps_op->u4_disp_wd[2] = 0; 3569 ps_op->u4_disp_ht[2] = 0; 3570 ps_op->u4_buffer_wd[2] = 0; 3571 ps_op->u4_buffer_ht[2] = 0; 3572 ps_op->u4_x_offset[2] = 0; 3573 ps_op->u4_y_offset[2] = 0; 3574 3575 ps_op->u4_disp_wd[1] <<= 1; 3576 ps_op->u4_buffer_wd[1] <<= 1; 3577 ps_op->u4_x_offset[1] <<= 1; 3578 } 3579 3580 return IV_SUCCESS; 3581 3582 } 3583 3584 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl, 3585 void *pv_api_ip, 3586 void *pv_api_op) 3587 { 3588 ih264d_ctl_get_vui_params_ip_t *ps_ip; 3589 ih264d_ctl_get_vui_params_op_t *ps_op; 3590 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3591 dec_seq_params_t *ps_sps; 3592 vui_t *ps_vui; 3593 WORD32 i; 3594 UWORD32 u4_size; 3595 3596 ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip; 3597 ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op; 3598 UNUSED(ps_ip); 3599 3600 u4_size = ps_op->u4_size; 3601 memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t)); 3602 ps_op->u4_size = u4_size; 3603 3604 if(NULL == ps_dec->ps_cur_sps) 3605 { 3606 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND; 3607 return IV_FAIL; 3608 } 3609 3610 ps_sps = ps_dec->ps_cur_sps; 3611 if((0 == ps_sps->u1_is_valid) 3612 || (0 == ps_sps->u1_vui_parameters_present_flag)) 3613 { 3614 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND; 3615 return IV_FAIL; 3616 } 3617 3618 ps_vui = &ps_sps->s_vui; 3619 3620 ps_op->u1_aspect_ratio_idc = ps_vui->u1_aspect_ratio_idc; 3621 ps_op->u2_sar_width = ps_vui->u2_sar_width; 3622 ps_op->u2_sar_height = ps_vui->u2_sar_height; 3623 ps_op->u1_overscan_appropriate_flag = ps_vui->u1_overscan_appropriate_flag; 3624 ps_op->u1_video_format = ps_vui->u1_video_format; 3625 ps_op->u1_video_full_range_flag = ps_vui->u1_video_full_range_flag; 3626 ps_op->u1_colour_primaries = ps_vui->u1_colour_primaries; 3627 ps_op->u1_tfr_chars = ps_vui->u1_tfr_chars; 3628 ps_op->u1_matrix_coeffs = ps_vui->u1_matrix_coeffs; 3629 ps_op->u1_cr_top_field = ps_vui->u1_cr_top_field; 3630 ps_op->u1_cr_bottom_field = ps_vui->u1_cr_bottom_field; 3631 ps_op->u4_num_units_in_tick = ps_vui->u4_num_units_in_tick; 3632 ps_op->u4_time_scale = ps_vui->u4_time_scale; 3633 ps_op->u1_fixed_frame_rate_flag = ps_vui->u1_fixed_frame_rate_flag; 3634 ps_op->u1_nal_hrd_params_present = ps_vui->u1_nal_hrd_params_present; 3635 ps_op->u1_vcl_hrd_params_present = ps_vui->u1_vcl_hrd_params_present; 3636 ps_op->u1_low_delay_hrd_flag = ps_vui->u1_low_delay_hrd_flag; 3637 ps_op->u1_pic_struct_present_flag = ps_vui->u1_pic_struct_present_flag; 3638 ps_op->u1_bitstream_restriction_flag = ps_vui->u1_bitstream_restriction_flag; 3639 ps_op->u1_mv_over_pic_boundaries_flag = ps_vui->u1_mv_over_pic_boundaries_flag; 3640 ps_op->u4_max_bytes_per_pic_denom = ps_vui->u4_max_bytes_per_pic_denom; 3641 ps_op->u4_max_bits_per_mb_denom = ps_vui->u4_max_bits_per_mb_denom; 3642 ps_op->u4_log2_max_mv_length_horz = ps_vui->u4_log2_max_mv_length_horz; 3643 ps_op->u4_log2_max_mv_length_vert = ps_vui->u4_log2_max_mv_length_vert; 3644 ps_op->u4_num_reorder_frames = ps_vui->u4_num_reorder_frames; 3645 ps_op->u4_max_dec_frame_buffering = ps_vui->u4_max_dec_frame_buffering; 3646 3647 return IV_SUCCESS; 3648 } 3649 3650 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3651 { 3652 ih264d_ctl_set_num_cores_ip_t *ps_ip; 3653 ih264d_ctl_set_num_cores_op_t *ps_op; 3654 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3655 3656 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 3657 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 3658 ps_op->u4_error_code = 0; 3659 ps_dec->u4_num_cores = ps_ip->u4_num_cores; 3660 if(ps_dec->u4_num_cores == 1) 3661 { 3662 ps_dec->u1_separate_parse = 0; 3663 } 3664 else 3665 { 3666 ps_dec->u1_separate_parse = 1; 3667 } 3668 3669 /*using only upto three threads currently*/ 3670 if(ps_dec->u4_num_cores > 3) 3671 ps_dec->u4_num_cores = 3; 3672 3673 return IV_SUCCESS; 3674 } 3675 3676 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 3677 ivd_video_decode_op_t *ps_dec_op) 3678 { 3679 if((ps_dec_op->u4_error_code & 0xff) 3680 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 3681 { 3682 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 3683 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 3684 } 3685 ps_dec_op->e_pic_type = ps_dec->i4_frametype; 3686 3687 ps_dec_op->u4_new_seq = 0; 3688 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 3689 ps_dec_op->u4_progressive_frame_flag = 3690 ps_dec->s_disp_op.u4_progressive_frame_flag; 3691 3692 ps_dec_op->u4_is_ref_flag = 1; 3693 if(ps_dec_op->u4_frame_decoded_flag) 3694 { 3695 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0) 3696 ps_dec_op->u4_is_ref_flag = 0; 3697 } 3698 3699 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format; 3700 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 3701 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 3702 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 3703 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 3704 } 3705 3706 /*****************************************************************************/ 3707 /* */ 3708 /* Function Name : ih264d_api_function */ 3709 /* */ 3710 /* Description : */ 3711 /* */ 3712 /* Inputs :iv_obj_t decoder handle */ 3713 /* :pv_api_ip pointer to input structure */ 3714 /* :pv_api_op pointer to output structure */ 3715 /* Outputs : */ 3716 /* Returns : void */ 3717 /* */ 3718 /* Issues : none */ 3719 /* */ 3720 /* Revision History: */ 3721 /* */ 3722 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3723 /* 22 10 2008 100356 Draft */ 3724 /* */ 3725 /*****************************************************************************/ 3726 IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl, 3727 void *pv_api_ip, 3728 void *pv_api_op) 3729 { 3730 UWORD32 command; 3731 UWORD32 *pu2_ptr_cmd; 3732 UWORD32 u4_api_ret; 3733 IV_API_CALL_STATUS_T e_status; 3734 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op); 3735 3736 if(e_status != IV_SUCCESS) 3737 { 3738 UWORD32 *ptr_err; 3739 3740 ptr_err = (UWORD32 *)pv_api_op; 3741 UNUSED(ptr_err); 3742 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1)); 3743 return IV_FAIL; 3744 } 3745 3746 pu2_ptr_cmd = (UWORD32 *)pv_api_ip; 3747 pu2_ptr_cmd++; 3748 3749 command = *pu2_ptr_cmd; 3750 // H264_DEC_DEBUG_PRINT("inside lib = %d\n",command); 3751 switch(command) 3752 { 3753 3754 case IVD_CMD_CREATE: 3755 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip, 3756 (void *)pv_api_op); 3757 break; 3758 case IVD_CMD_DELETE: 3759 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip, 3760 (void *)pv_api_op); 3761 break; 3762 3763 case IVD_CMD_VIDEO_DECODE: 3764 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip, 3765 (void *)pv_api_op); 3766 break; 3767 3768 case IVD_CMD_GET_DISPLAY_FRAME: 3769 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip, 3770 (void *)pv_api_op); 3771 3772 break; 3773 3774 case IVD_CMD_SET_DISPLAY_FRAME: 3775 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip, 3776 (void *)pv_api_op); 3777 3778 break; 3779 3780 case IVD_CMD_REL_DISPLAY_FRAME: 3781 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip, 3782 (void *)pv_api_op); 3783 break; 3784 3785 case IVD_CMD_VIDEO_CTL: 3786 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip, 3787 (void *)pv_api_op); 3788 break; 3789 default: 3790 u4_api_ret = IV_FAIL; 3791 break; 3792 } 3793 3794 return u4_api_ret; 3795 } 3796
