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      1 This file is a partial list of people who have contributed to the LLVM
      2 project.  If you have contributed a patch or made some other contribution to
      3 LLVM, please submit a patch to this file to add yourself, and it will be
      4 done!
      5 
      6 The list is sorted by surname and formatted to allow easy grepping and
      7 beautification by scripts.  The fields are: name (N), email (E), web-address
      8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
      9 (S), and (I) IRC handle.
     10 
     11 
     12 N: Vikram Adve
     13 E: vadve (a] cs.uiuc.edu
     14 W: http://www.cs.uiuc.edu/~vadve/
     15 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
     16 
     17 N: Owen Anderson
     18 E: resistor (a] mac.com
     19 D: LCSSA pass and related LoopUnswitch work
     20 D: GVNPRE pass, DataLayout refactoring, random improvements
     21 
     22 N: Henrik Bach
     23 D: MingW Win32 API portability layer
     24 
     25 N: Aaron Ballman
     26 E: aaron (a] aaronballman.com
     27 D: __declspec attributes, Windows support, general bug fixing
     28 
     29 N: Nate Begeman
     30 E: natebegeman (a] mac.com
     31 D: PowerPC backend developer
     32 D: Target-independent code generator and analysis improvements
     33 
     34 N: Daniel Berlin
     35 E: dberlin (a] dberlin.org
     36 D: ET-Forest implementation.
     37 D: Sparse bitmap
     38 
     39 N: David Blaikie
     40 E: dblaikie (a] gmail.com
     41 D: General bug fixing/fit & finish, mostly in Clang
     42 
     43 N: Neil Booth
     44 E: neil (a] daikokuya.co.uk
     45 D: APFloat implementation.
     46 
     47 N: Misha Brukman
     48 E: brukman+llvm (a] uiuc.edu
     49 W: http://misha.brukman.net
     50 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
     51 D: Incremental bitcode loader
     52 
     53 N: Cameron Buschardt
     54 E: buschard (a] uiuc.edu
     55 D: The `mem2reg' pass - promotes values stored in memory to registers
     56 
     57 N: Brendon Cahoon
     58 E: bcahoon (a] codeaurora.org
     59 D: Loop unrolling with run-time trip counts.
     60 
     61 N: Chandler Carruth
     62 E: chandlerc (a] gmail.com
     63 E: chandlerc (a] google.com
     64 D: Hashing algorithms and interfaces
     65 D: Inline cost analysis
     66 D: Machine block placement pass
     67 D: SROA
     68 
     69 N: Casey Carter
     70 E: ccarter (a] uiuc.edu
     71 D: Fixes to the Reassociation pass, various improvement patches
     72 
     73 N: Evan Cheng
     74 E: evan.cheng (a] apple.com
     75 D: ARM and X86 backends
     76 D: Instruction scheduler improvements
     77 D: Register allocator improvements
     78 D: Loop optimizer improvements
     79 D: Target-independent code generator improvements
     80 
     81 N: Dan Villiom Podlaski Christiansen
     82 E: danchr (a] gmail.com
     83 E: danchr (a] cs.au.dk
     84 W: http://villiom.dk
     85 D: LLVM Makefile improvements
     86 D: Clang diagnostic & driver tweaks
     87 S: Aarhus, Denmark
     88 
     89 N: Jeff Cohen
     90 E: jeffc (a] jolt-lang.org
     91 W: http://jolt-lang.org
     92 D: Native Win32 API portability layer
     93 
     94 N: John T. Criswell
     95 E: criswell (a] uiuc.edu
     96 D: Original Autoconf support, documentation improvements, bug fixes
     97 
     98 N: Anshuman Dasgupta
     99 E: adasgupt (a] codeaurora.org
    100 D: Deterministic finite automaton based infrastructure for VLIW packetization
    101 
    102 N: Stefanus Du Toit
    103 E: stefanus.du.toit (a] intel.com
    104 D: Bug fixes and minor improvements
    105 
    106 N: Rafael Avila de Espindola
    107 E: rafael.espindola (a] gmail.com
    108 D: The ARM backend
    109 
    110 N: Dave Estes
    111 E: cestes (a] codeaurora.org
    112 D: AArch64 machine description for Cortex-A53
    113 
    114 N: Alkis Evlogimenos
    115 E: alkis (a] evlogimenos.com
    116 D: Linear scan register allocator, many codegen improvements, Java frontend
    117 
    118 N: Hal Finkel
    119 E: hfinkel (a] anl.gov
    120 D: Basic-block autovectorization, PowerPC backend improvements
    121 
    122 N: Eric Fiselier
    123 E: eric (a] efcs.ca
    124 D: LIT patches and documentation.
    125 
    126 N: Ryan Flynn
    127 E: pizza (a] parseerror.com
    128 D: Miscellaneous bug fixes
    129 
    130 N: Brian Gaeke
    131 E: gaeke (a] uiuc.edu
    132 W: http://www.students.uiuc.edu/~gaeke/
    133 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
    134 D: Dynamic trace optimizer
    135 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
    136 
    137 N: Nicolas Geoffray
    138 E: nicolas.geoffray (a] lip6.fr
    139 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
    140 D: PPC backend fixes for Linux
    141 
    142 N: Louis Gerbarg
    143 E: lgg (a] apple.com
    144 D: Portions of the PowerPC backend
    145 
    146 N: Saem Ghani
    147 E: saemghani (a] gmail.com
    148 D: Callgraph class cleanups
    149 
    150 N: Mikhail Glushenkov
    151 E: foldr (a] codedgers.com
    152 D: Author of llvmc2
    153 
    154 N: Dan Gohman
    155 E: sunfish (a] mozilla.com
    156 D: Miscellaneous bug fixes
    157 D: WebAssembly Backend
    158 
    159 N: David Goodwin
    160 E: david (a] goodwinz.net
    161 D: Thumb-2 code generator
    162 
    163 N: David Greene
    164 E: greened (a] obbligato.org
    165 D: Miscellaneous bug fixes
    166 D: Register allocation refactoring
    167 
    168 N: Gabor Greif
    169 E: ggreif (a] gmail.com
    170 D: Improvements for space efficiency
    171 
    172 N: James Grosbach
    173 E: grosbach (a] apple.com
    174 I: grosbach
    175 D: SjLj exception handling support
    176 D: General fixes and improvements for the ARM back-end
    177 D: MCJIT
    178 D: ARM integrated assembler and assembly parser
    179 D: Led effort for the backend formerly known as ARM64
    180 
    181 N: Lang Hames
    182 E: lhames (a] gmail.com
    183 D: PBQP-based register allocator
    184 
    185 N: Gordon Henriksen
    186 E: gordonhenriksen (a] mac.com
    187 D: Pluggable GC support
    188 D: C interface
    189 D: Ocaml bindings
    190 
    191 N: Raul Fernandes Herbster
    192 E: raul (a] dsc.ufcg.edu.br
    193 D: JIT support for ARM
    194 
    195 N: Paolo Invernizzi
    196 E: arathorn (a] fastwebnet.it
    197 D: Visual C++ compatibility fixes
    198 
    199 N: Patrick Jenkins
    200 E: patjenk (a] wam.umd.edu
    201 D: Nightly Tester
    202 
    203 N: Dale Johannesen
    204 E: dalej (a] apple.com
    205 D: ARM constant islands improvements
    206 D: Tail merging improvements
    207 D: Rewrite X87 back end
    208 D: Use APFloat for floating point constants widely throughout compiler
    209 D: Implement X87 long double
    210 
    211 N: Brad Jones
    212 E: kungfoomaster (a] nondot.org
    213 D: Support for packed types
    214 
    215 N: Rod Kay
    216 E: rkay (a] auroraux.org
    217 D: Author of LLVM Ada bindings
    218 
    219 N: Eric Kidd
    220 W: http://randomhacks.net/
    221 D: llvm-config script
    222 
    223 N: Anton Korobeynikov
    224 E: asl (a] math.spbu.ru
    225 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
    226 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
    227 D: Switch lowering refactoring
    228 
    229 N: Sumant Kowshik
    230 E: kowshik (a] uiuc.edu
    231 D: Author of the original C backend
    232 
    233 N: Benjamin Kramer
    234 E: benny.kra (a] gmail.com
    235 D: Miscellaneous bug fixes
    236 
    237 N: Sundeep Kushwaha
    238 E: sundeepk (a] codeaurora.org
    239 D: Implemented DFA-based target independent VLIW packetizer
    240 
    241 N: Christopher Lamb
    242 E: christopher.lamb (a] gmail.com
    243 D: aligned load/store support, parts of noalias and restrict support
    244 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
    245 D: address spaces
    246 
    247 N: Jim Laskey
    248 E: jlaskey (a] apple.com
    249 D: Improvements to the PPC backend, instruction scheduling
    250 D: Debug and Dwarf implementation
    251 D: Auto upgrade mangler
    252 D: llvm-gcc4 svn wrangler
    253 
    254 N: Chris Lattner
    255 E: sabre (a] nondot.org
    256 W: http://nondot.org/~sabre/
    257 D: Primary architect of LLVM
    258 
    259 N: Tanya Lattner (Tanya Brethour)
    260 E: tonic (a] nondot.org
    261 W: http://nondot.org/~tonic/
    262 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
    263 D: Modulo scheduling in the SparcV9 backend
    264 D: Release manager (1.7+)
    265 
    266 N: Sylvestre Ledru
    267 E: sylvestre (a] debian.org
    268 W: http://sylvestre.ledru.info/
    269 W: http://llvm.org/apt/
    270 D: Debian and Ubuntu packaging
    271 D: Continuous integration with jenkins
    272 
    273 N: Andrew Lenharth
    274 E: alenhar2 (a] cs.uiuc.edu
    275 W: http://www.lenharth.org/~andrewl/
    276 D: Alpha backend
    277 D: Sampling based profiling
    278 
    279 N: Nick Lewycky
    280 E: nicholas (a] mxc.ca
    281 D: PredicateSimplifier pass
    282 
    283 N: Tony Linthicum, et. al.
    284 E: tlinth (a] codeaurora.org
    285 D: Backend for Qualcomm's Hexagon VLIW processor.
    286 
    287 N: Bruno Cardoso Lopes
    288 E: bruno.cardoso (a] gmail.com
    289 I: bruno
    290 W: http://brunocardoso.cc
    291 D: Mips backend
    292 D: Random ARM integrated assembler and assembly parser improvements
    293 D: General X86 AVX1 support
    294 
    295 N: Duraid Madina
    296 E: duraid (a] octopus.com.au
    297 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
    298 D: IA64 backend, BigBlock register allocator
    299 
    300 N: John McCall
    301 E: rjmccall (a] apple.com
    302 D: Clang semantic analysis and IR generation
    303 
    304 N: Michael McCracken
    305 E: michael.mccracken (a] gmail.com
    306 D: Line number support for llvmgcc
    307 
    308 N: Vladimir Merzliakov
    309 E: wanderer (a] rsu.ru
    310 D: Test suite fixes for FreeBSD
    311 
    312 N: Scott Michel
    313 E: scottm (a] aero.org
    314 D: Added STI Cell SPU backend.
    315 
    316 N: Kai Nacke
    317 E: kai (a] redstar.de
    318 D: Support for implicit TLS model used with MS VC runtime
    319 D: Dumping of Win64 EH structures
    320 
    321 N: Takumi Nakamura
    322 E: geek4civic (a] gmail.com
    323 E: chapuni (a] hf.rim.or.jp
    324 D: Cygwin and MinGW support.
    325 D: Win32 tweaks.
    326 S: Yokohama, Japan
    327 
    328 N: Edward O'Callaghan
    329 E: eocallaghan (a] auroraux.org
    330 W: http://www.auroraux.org
    331 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
    332 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
    333 D: and error clean ups.
    334 
    335 N: Morten Ofstad
    336 E: morten (a] hue.no
    337 D: Visual C++ compatibility fixes
    338 
    339 N: Jakob Stoklund Olesen
    340 E: stoklund (a] 2pi.dk
    341 D: Machine code verifier
    342 D: Blackfin backend
    343 D: Fast register allocator
    344 D: Greedy register allocator
    345 
    346 N: Richard Osborne
    347 E: richard (a] xmos.com
    348 D: XCore backend
    349 
    350 N: Piotr Padlewski
    351 E: piotr.padlewski (a] gmail.com
    352 D: !invariant.group metadata and other intrinsics for devirtualization in clang
    353 
    354 N: Devang Patel
    355 E: dpatel (a] apple.com
    356 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
    357 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
    358 D: Optimizer improvements, Loop Index Split
    359 
    360 N: Ana Pazos
    361 E: apazos (a] codeaurora.org
    362 D: Fixes and improvements to the AArch64 backend
    363 
    364 N: Wesley Peck
    365 E: peckw (a] wesleypeck.com
    366 W: http://wesleypeck.com/
    367 D: MicroBlaze backend
    368 
    369 N: Francois Pichet
    370 E: pichet2000 (a] gmail.com
    371 D: MSVC support
    372 
    373 N: Vladimir Prus
    374 W: http://vladimir_prus.blogspot.com
    375 E: ghost (a] cs.msu.su
    376 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
    377 
    378 N: Kalle Raiskila
    379 E: kalle.rasikila (a] nokia.com
    380 D: Some bugfixes to CellSPU
    381 
    382 N: Xerxes Ranby
    383 E: xerxes (a] zafena.se
    384 D: Cmake dependency chain and various bug fixes
    385 
    386 N: Alex Rosenberg
    387 E: alexr (a] leftfield.org
    388 I: arosenberg
    389 D: ARM calling conventions rewrite, hard float support
    390 
    391 N: Chad Rosier
    392 E: mcrosier (a] codeaurora.org
    393 I: mcrosier
    394 D: AArch64 fast instruction selection pass
    395 D: Fixes and improvements to the ARM fast-isel pass
    396 D: Fixes and improvements to the AArch64 backend
    397 
    398 N: Nadav Rotem
    399 E: nadav.rotem (a] me.com
    400 D: X86 code generation improvements, Loop Vectorizer.
    401 
    402 N: Roman Samoilov
    403 E: roman (a] codedgers.com
    404 D: MSIL backend
    405 
    406 N: Duncan Sands
    407 E: baldrick (a] free.fr
    408 I: baldrick
    409 D: Ada support in llvm-gcc
    410 D: Dragonegg plugin
    411 D: Exception handling improvements
    412 D: Type legalizer rewrite
    413 
    414 N: Ruchira Sasanka
    415 E: sasanka (a] uiuc.edu
    416 D: Graph coloring register allocator for the Sparc64 backend
    417 
    418 N: Arnold Schwaighofer
    419 E: arnold.schwaighofer (a] gmail.com
    420 D: Tail call optimization for the x86 backend
    421 
    422 N: Shantonu Sen
    423 E: ssen (a] apple.com
    424 D: Miscellaneous bug fixes
    425 
    426 N: Anand Shukla
    427 E: ashukla (a] cs.uiuc.edu
    428 D: The `paths' pass
    429 
    430 N: Michael J. Spencer
    431 E: bigcheesegs (a] gmail.com
    432 D: Shepherding Windows COFF support into MC.
    433 D: Lots of Windows stuff.
    434 
    435 N: Reid Spencer
    436 E: rspencer (a] reidspencer.com
    437 W: http://reidspencer.com/
    438 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
    439 
    440 N: Alp Toker
    441 E: alp (a] nuanti.com
    442 W: http://atoker.com/
    443 D: C++ frontend next generation standards implementation
    444 
    445 N: Craig Topper
    446 E: craig.topper (a] gmail.com
    447 D: X86 codegen and disassembler improvements. AVX2 support.
    448 
    449 N: Edwin Torok
    450 E: edwintorok (a] gmail.com
    451 D: Miscellaneous bug fixes
    452 
    453 N: Adam Treat
    454 E: manyoso (a] yahoo.com
    455 D: C++ bugs filed, and C++ front-end bug fixes.
    456 
    457 N: Lauro Ramos Venancio
    458 E: lauro.venancio (a] indt.org.br
    459 D: ARM backend improvements
    460 D: Thread Local Storage implementation
    461 
    462 N: Bill Wendling
    463 I: wendling
    464 E: isanbard (a] gmail.com
    465 D: Release manager, IR Linker, LTO
    466 D: Bunches of stuff
    467 
    468 N: Bob Wilson
    469 E: bob.wilson (a] acm.org
    470 D: Advanced SIMD (NEON) support in the ARM backend.
    471 
    472