1 //===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // TableGen definitions for instructions which are available only on Cayman 11 // family GPUs. 12 // 13 //===----------------------------------------------------------------------===// 14 15 def isCayman : Predicate<"Subtarget->hasCaymanISA()">; 16 17 //===----------------------------------------------------------------------===// 18 // Cayman Instructions 19 //===----------------------------------------------------------------------===// 20 21 let Predicates = [isCayman] in { 22 23 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24", 24 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU 25 >; 26 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24", 27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU 28 >; 29 30 def : IMad24Pat<MULADD_INT24_cm>; 31 32 let isVector = 1 in { 33 34 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 35 36 def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 37 def MULHI_INT_cm : MULHI_INT_Common<0x90>; 38 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 39 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 40 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>; 41 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>; 42 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>; 43 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>; 44 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>; 45 def SIN_cm : SIN_Common<0x8D>; 46 def COS_cm : COS_Common<0x8E>; 47 } // End isVector = 1 48 49 def : RsqPat<RECIPSQRT_IEEE_cm, f32>; 50 51 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>; 52 53 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>; 54 55 // RECIP_UINT emulation for Cayman 56 // The multiplication scales from [0,1] to the unsigned integer range 57 def : Pat < 58 (AMDGPUurecip i32:$src0), 59 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)), 60 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1))) 61 >; 62 63 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> { 64 let ADDR = 0; 65 let POP_COUNT = 0; 66 let COUNT = 0; 67 } 68 69 70 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>; 71 72 class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> : 73 CF_MEM_RAT_CACHELESS <0x14, 0, mask, 74 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr), 75 "STORE_DWORD $rw_gpr, $index_gpr", 76 [(global_store vt:$rw_gpr, i32:$index_gpr)]> { 77 let eop = 0; // This bit is not used on Cayman. 78 } 79 80 def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>; 81 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>; 82 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>; 83 84 def RAT_STORE_TYPED_cm: CF_MEM_RAT_STORE_TYPED<0> { 85 let eop = 0; // This bit is not used on Cayman. 86 } 87 88 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 89 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> { 90 91 // Static fields 92 let VC_INST = 0; 93 let FETCH_TYPE = 2; 94 let FETCH_WHOLE_QUAD = 0; 95 let BUFFER_ID = buffer_id; 96 let SRC_REL = 0; 97 // XXX: We can infer this field based on the SRC_GPR. This would allow us 98 // to store vertex addresses in any channel, not just X. 99 let SRC_SEL_X = 0; 100 let SRC_SEL_Y = 0; 101 let STRUCTURED_READ = 0; 102 let LDS_REQ = 0; 103 let COALESCED_READ = 0; 104 105 let Inst{31-0} = Word0; 106 } 107 108 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern> 109 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 110 (outs R600_TReg32_X:$dst_gpr), pattern> { 111 112 let DST_SEL_X = 0; 113 let DST_SEL_Y = 7; // Masked 114 let DST_SEL_Z = 7; // Masked 115 let DST_SEL_W = 7; // Masked 116 let DATA_FORMAT = 1; // FMT_8 117 } 118 119 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern> 120 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 121 (outs R600_TReg32_X:$dst_gpr), pattern> { 122 let DST_SEL_X = 0; 123 let DST_SEL_Y = 7; // Masked 124 let DST_SEL_Z = 7; // Masked 125 let DST_SEL_W = 7; // Masked 126 let DATA_FORMAT = 5; // FMT_16 127 128 } 129 130 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern> 131 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 132 (outs R600_TReg32_X:$dst_gpr), pattern> { 133 134 let DST_SEL_X = 0; 135 let DST_SEL_Y = 7; // Masked 136 let DST_SEL_Z = 7; // Masked 137 let DST_SEL_W = 7; // Masked 138 let DATA_FORMAT = 0xD; // COLOR_32 139 140 // This is not really necessary, but there were some GPU hangs that appeared 141 // to be caused by ALU instructions in the next instruction group that wrote 142 // to the $src_gpr registers of the VTX_READ. 143 // e.g. 144 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 145 // %T2_X<def> = MOV %ZERO 146 //Adding this constraint prevents this from happening. 147 let Constraints = "$src_gpr.ptr = $dst_gpr"; 148 } 149 150 class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern> 151 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id, 152 (outs R600_Reg64:$dst_gpr), pattern> { 153 154 let DST_SEL_X = 0; 155 let DST_SEL_Y = 1; 156 let DST_SEL_Z = 7; 157 let DST_SEL_W = 7; 158 let DATA_FORMAT = 0x1D; // COLOR_32_32 159 } 160 161 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern> 162 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 163 (outs R600_Reg128:$dst_gpr), pattern> { 164 165 let DST_SEL_X = 0; 166 let DST_SEL_Y = 1; 167 let DST_SEL_Z = 2; 168 let DST_SEL_W = 3; 169 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 170 171 // XXX: Need to force VTX_READ_128 instructions to write to the same register 172 // that holds its buffer address to avoid potential hangs. We can't use 173 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 174 // registers are different sizes. 175 } 176 177 //===----------------------------------------------------------------------===// 178 // VTX Read from parameter memory space 179 //===----------------------------------------------------------------------===// 180 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0, 181 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 182 >; 183 184 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0, 185 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 186 >; 187 188 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0, 189 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 190 >; 191 192 def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0, 193 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 194 >; 195 196 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0, 197 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 198 >; 199 200 //===----------------------------------------------------------------------===// 201 // VTX Read from global memory space 202 //===----------------------------------------------------------------------===// 203 204 // 8-bit reads 205 def VTX_READ_ID1_8_cm : VTX_READ_8_cm <1, 206 [(set i32:$dst_gpr, (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr))] 207 >; 208 209 // 16-bit reads 210 def VTX_READ_ID1_16_cm : VTX_READ_16_cm <1, 211 [(set i32:$dst_gpr, (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr))] 212 >; 213 214 // 32-bit reads 215 def VTX_READ_ID1_32_cm : VTX_READ_32_cm <1, 216 [(set i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] 217 >; 218 219 // 64-bit reads 220 def VTX_READ_ID1_64_cm : VTX_READ_64_cm <1, 221 [(set v2i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] 222 >; 223 224 // 128-bit reads 225 def VTX_READ_ID1_128_cm : VTX_READ_128_cm <1, 226 [(set v4i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] 227 >; 228 229 // 8-bit reads 230 def VTX_READ_ID2_8_cm : VTX_READ_8_cm <2, 231 [(set i32:$dst_gpr, (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr))] 232 >; 233 234 // 16-bit reads 235 def VTX_READ_ID2_16_cm : VTX_READ_16_cm <2, 236 [(set i32:$dst_gpr, (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr))] 237 >; 238 239 // 32-bit reads 240 def VTX_READ_ID2_32_cm : VTX_READ_32_cm <2, 241 [(set i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] 242 >; 243 244 // 64-bit reads 245 def VTX_READ_ID2_64_cm : VTX_READ_64_cm <2, 246 [(set v2i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] 247 >; 248 249 // 128-bit reads 250 def VTX_READ_ID2_128_cm : VTX_READ_128_cm <2, 251 [(set v4i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] 252 >; 253 254 } // End isCayman 255 256
