1 //===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // TableGen definitions for instructions which are: 11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs 12 // - Available only on Evergreen family GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 def isEG : Predicate< 17 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 18 "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " 19 "!Subtarget->hasCaymanISA()" 20 >; 21 22 def isEGorCayman : Predicate< 23 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 24 "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" 25 >; 26 27 //===----------------------------------------------------------------------===// 28 // Evergreen / Cayman store instructions 29 //===----------------------------------------------------------------------===// 30 31 let Predicates = [isEGorCayman] in { 32 33 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 34 string name, list<dag> pattern> 35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 36 "MEM_RAT_CACHELESS "#name, pattern>; 37 38 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name, 39 list<dag> pattern> 40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins, 41 "MEM_RAT "#name, pattern>; 42 43 class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop> 44 : CF_MEM_RAT <0x1, ?, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr, 45 i32imm:$rat_id, InstFlag:$eop), 46 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr" 47 #!if(has_eop, ", $eop", ""), 48 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr, 49 R600_Reg128:$index_gpr, 50 (i32 imm:$rat_id))]>; 51 52 def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 53 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 54 "MSKOR $rw_gpr.XW, $index_gpr", 55 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 56 > { 57 let eop = 0; 58 } 59 60 } // End let Predicates = [isEGorCayman] 61 62 //===----------------------------------------------------------------------===// 63 // Evergreen Only instructions 64 //===----------------------------------------------------------------------===// 65 66 let Predicates = [isEG] in { 67 68 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 69 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 70 71 def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 72 def MULHI_INT_eg : MULHI_INT_Common<0x90>; 73 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 74 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 75 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 76 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 77 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 78 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 79 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 80 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 81 def : RsqPat<RECIPSQRT_IEEE_eg, f32>; 82 def SIN_eg : SIN_Common<0x8D>; 83 def COS_eg : COS_Common<0x8E>; 84 85 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 86 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; 87 88 //===----------------------------------------------------------------------===// 89 // Memory read/write instructions 90 //===----------------------------------------------------------------------===// 91 92 let usesCustomInserter = 1 in { 93 94 // 32-bit store 95 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 96 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 97 "STORE_RAW $rw_gpr, $index_gpr, $eop", 98 [(global_store i32:$rw_gpr, i32:$index_gpr)] 99 >; 100 101 // 64-bit store 102 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 103 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 104 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 105 [(global_store v2i32:$rw_gpr, i32:$index_gpr)] 106 >; 107 108 //128-bit store 109 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 110 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 111 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 112 [(global_store v4i32:$rw_gpr, i32:$index_gpr)] 113 >; 114 115 def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>; 116 117 } // End usesCustomInserter = 1 118 119 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 120 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> { 121 122 // Static fields 123 let VC_INST = 0; 124 let FETCH_TYPE = 2; 125 let FETCH_WHOLE_QUAD = 0; 126 let BUFFER_ID = buffer_id; 127 let SRC_REL = 0; 128 // XXX: We can infer this field based on the SRC_GPR. This would allow us 129 // to store vertex addresses in any channel, not just X. 130 let SRC_SEL_X = 0; 131 132 let Inst{31-0} = Word0; 133 } 134 135 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern> 136 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 137 (outs R600_TReg32_X:$dst_gpr), pattern> { 138 139 let MEGA_FETCH_COUNT = 1; 140 let DST_SEL_X = 0; 141 let DST_SEL_Y = 7; // Masked 142 let DST_SEL_Z = 7; // Masked 143 let DST_SEL_W = 7; // Masked 144 let DATA_FORMAT = 1; // FMT_8 145 } 146 147 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern> 148 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 149 (outs R600_TReg32_X:$dst_gpr), pattern> { 150 let MEGA_FETCH_COUNT = 2; 151 let DST_SEL_X = 0; 152 let DST_SEL_Y = 7; // Masked 153 let DST_SEL_Z = 7; // Masked 154 let DST_SEL_W = 7; // Masked 155 let DATA_FORMAT = 5; // FMT_16 156 157 } 158 159 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 160 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 161 (outs R600_TReg32_X:$dst_gpr), pattern> { 162 163 let MEGA_FETCH_COUNT = 4; 164 let DST_SEL_X = 0; 165 let DST_SEL_Y = 7; // Masked 166 let DST_SEL_Z = 7; // Masked 167 let DST_SEL_W = 7; // Masked 168 let DATA_FORMAT = 0xD; // COLOR_32 169 170 // This is not really necessary, but there were some GPU hangs that appeared 171 // to be caused by ALU instructions in the next instruction group that wrote 172 // to the $src_gpr registers of the VTX_READ. 173 // e.g. 174 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 175 // %T2_X<def> = MOV %ZERO 176 //Adding this constraint prevents this from happening. 177 let Constraints = "$src_gpr.ptr = $dst_gpr"; 178 } 179 180 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern> 181 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id, 182 (outs R600_Reg64:$dst_gpr), pattern> { 183 184 let MEGA_FETCH_COUNT = 8; 185 let DST_SEL_X = 0; 186 let DST_SEL_Y = 1; 187 let DST_SEL_Z = 7; 188 let DST_SEL_W = 7; 189 let DATA_FORMAT = 0x1D; // COLOR_32_32 190 } 191 192 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 193 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 194 (outs R600_Reg128:$dst_gpr), pattern> { 195 196 let MEGA_FETCH_COUNT = 16; 197 let DST_SEL_X = 0; 198 let DST_SEL_Y = 1; 199 let DST_SEL_Z = 2; 200 let DST_SEL_W = 3; 201 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 202 203 // XXX: Need to force VTX_READ_128 instructions to write to the same register 204 // that holds its buffer address to avoid potential hangs. We can't use 205 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 206 // registers are different sizes. 207 } 208 209 //===----------------------------------------------------------------------===// 210 // VTX Read from parameter memory space 211 //===----------------------------------------------------------------------===// 212 213 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <3, 214 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 215 >; 216 217 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <3, 218 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 219 >; 220 221 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <3, 222 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 223 >; 224 225 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <3, 226 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 227 >; 228 229 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <3, 230 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 231 >; 232 233 //===----------------------------------------------------------------------===// 234 // VTX Read from global memory space 235 //===----------------------------------------------------------------------===// 236 237 // 8-bit reads 238 def VTX_READ_ID1_8_eg : VTX_READ_8_eg <1, 239 [(set i32:$dst_gpr, (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr))] 240 >; 241 242 // 16-bit reads 243 def VTX_READ_ID1_16_eg : VTX_READ_16_eg <1, 244 [(set i32:$dst_gpr, (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr))] 245 >; 246 247 // 32-bit reads 248 def VTX_READ_ID1_32_eg : VTX_READ_32_eg <1, 249 [(set i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] 250 >; 251 252 // 64-bit reads 253 def VTX_READ_ID1_64_eg : VTX_READ_64_eg <1, 254 [(set v2i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] 255 >; 256 257 // 128-bit reads 258 def VTX_READ_ID1_128_eg : VTX_READ_128_eg <1, 259 [(set v4i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] 260 >; 261 262 // 8-bit reads 263 def VTX_READ_ID2_8_eg : VTX_READ_8_eg <2, 264 [(set i32:$dst_gpr, (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr))] 265 >; 266 267 // 16-bit reads 268 def VTX_READ_ID2_16_eg : VTX_READ_16_eg <2, 269 [(set i32:$dst_gpr, (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr))] 270 >; 271 272 // 32-bit reads 273 def VTX_READ_ID2_32_eg : VTX_READ_32_eg <2, 274 [(set i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] 275 >; 276 277 // 64-bit reads 278 def VTX_READ_ID2_64_eg : VTX_READ_64_eg <2, 279 [(set v2i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] 280 >; 281 282 // 128-bit reads 283 def VTX_READ_ID2_128_eg : VTX_READ_128_eg <2, 284 [(set v4i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] 285 >; 286 287 } // End Predicates = [isEG] 288 289 //===----------------------------------------------------------------------===// 290 // Evergreen / Cayman Instructions 291 //===----------------------------------------------------------------------===// 292 293 let Predicates = [isEGorCayman] in { 294 295 // Should be predicated on FeatureFP64 296 // def FMA_64 : R600_3OP < 297 // 0xA, "FMA_64", 298 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 299 // >; 300 301 // BFE_UINT - bit_extract, an optimization for mask and shift 302 // Src0 = Input 303 // Src1 = Offset 304 // Src2 = Width 305 // 306 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 307 // 308 // Example Usage: 309 // (Offset, Width) 310 // 311 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 312 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 313 // (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 314 // (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 315 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 316 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 317 VecALU 318 >; 319 320 def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 321 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 322 VecALU 323 >; 324 325 def : BFEPattern <BFE_UINT_eg, MOV_IMM_I32>; 326 327 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 328 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 329 VecALU 330 >; 331 332 def : Pat<(i32 (sext_inreg i32:$src, i1)), 333 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 334 def : Pat<(i32 (sext_inreg i32:$src, i8)), 335 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 336 def : Pat<(i32 (sext_inreg i32:$src, i16)), 337 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 338 339 defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>; 340 341 def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 342 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 343 VecALU 344 >; 345 346 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 347 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 348 >; 349 350 def : UMad24Pat<MULADD_UINT24_eg>; 351 352 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 353 def : ROTRPattern <BIT_ALIGN_INT_eg>; 354 def MULADD_eg : MULADD_Common<0x14>; 355 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 356 def FMA_eg : FMA_Common<0x7>; 357 def ASHR_eg : ASHR_Common<0x15>; 358 def LSHR_eg : LSHR_Common<0x16>; 359 def LSHL_eg : LSHL_Common<0x17>; 360 def CNDE_eg : CNDE_Common<0x19>; 361 def CNDGT_eg : CNDGT_Common<0x1A>; 362 def CNDGE_eg : CNDGE_Common<0x1B>; 363 def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 364 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 365 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 366 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 367 >; 368 def DOT4_eg : DOT4_Common<0xBE>; 369 defm CUBE_eg : CUBE_Common<0xC0>; 370 371 def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 372 373 def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; 374 def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; 375 376 def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>; 377 def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>; 378 379 let hasSideEffects = 1 in { 380 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 381 } 382 383 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 384 let Pattern = []; 385 let Itinerary = AnyALU; 386 } 387 388 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 389 390 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 391 let Pattern = []; 392 } 393 394 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 395 396 def GROUP_BARRIER : InstR600 < 397 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>, 398 R600ALU_Word0, 399 R600ALU_Word1_OP2 <0x54> { 400 401 let dst = 0; 402 let dst_rel = 0; 403 let src0 = 0; 404 let src0_rel = 0; 405 let src0_neg = 0; 406 let src0_abs = 0; 407 let src1 = 0; 408 let src1_rel = 0; 409 let src1_neg = 0; 410 let src1_abs = 0; 411 let write = 0; 412 let omod = 0; 413 let clamp = 0; 414 let last = 1; 415 let bank_swizzle = 0; 416 let pred_sel = 0; 417 let update_exec_mask = 0; 418 let update_pred = 0; 419 420 let Inst{31-0} = Word0; 421 let Inst{63-32} = Word1; 422 423 let ALUInst = 1; 424 } 425 426 def : Pat < 427 (int_AMDGPU_barrier_global), 428 (GROUP_BARRIER) 429 >; 430 431 //===----------------------------------------------------------------------===// 432 // LDS Instructions 433 //===----------------------------------------------------------------------===// 434 class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 435 list<dag> pattern = []> : 436 437 InstR600 <outs, ins, asm, pattern, XALU>, 438 R600_ALU_LDS_Word0, 439 R600LDS_Word1 { 440 441 bits<6> offset = 0; 442 let lds_op = op; 443 444 let Word1{27} = offset{0}; 445 let Word1{12} = offset{1}; 446 let Word1{28} = offset{2}; 447 let Word1{31} = offset{3}; 448 let Word0{12} = offset{4}; 449 let Word0{25} = offset{5}; 450 451 452 let Inst{31-0} = Word0; 453 let Inst{63-32} = Word1; 454 455 let ALUInst = 1; 456 let HasNativeOperands = 1; 457 let UseNamedOperandTable = 1; 458 } 459 460 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 461 lds_op, 462 (outs R600_Reg32:$dst), 463 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 464 LAST:$last, R600_Pred:$pred_sel, 465 BANK_SWIZZLE:$bank_swizzle), 466 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 467 pattern 468 > { 469 470 let src1 = 0; 471 let src1_rel = 0; 472 let src2 = 0; 473 let src2_rel = 0; 474 475 let usesCustomInserter = 1; 476 let LDS_1A = 1; 477 let DisableEncoding = "$dst"; 478 } 479 480 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 481 string dst =""> : 482 R600_LDS < 483 lds_op, outs, 484 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 485 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 486 LAST:$last, R600_Pred:$pred_sel, 487 BANK_SWIZZLE:$bank_swizzle), 488 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 489 pattern 490 > { 491 492 field string BaseOp; 493 494 let src2 = 0; 495 let src2_rel = 0; 496 let LDS_1A1D = 1; 497 } 498 499 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 500 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 501 let BaseOp = name; 502 } 503 504 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 505 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> { 506 507 let BaseOp = name; 508 let usesCustomInserter = 1; 509 let DisableEncoding = "$dst"; 510 } 511 512 class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 513 string dst =""> : 514 R600_LDS < 515 lds_op, outs, 516 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 517 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 518 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 519 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 520 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 521 pattern> { 522 523 field string BaseOp; 524 525 let LDS_1A1D = 0; 526 let LDS_1A2D = 1; 527 } 528 529 class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 530 R600_LDS_1A2D <lds_op, (outs), name, pattern> { 531 let BaseOp = name; 532 } 533 534 class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> : 535 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> { 536 537 let BaseOp = name; 538 let usesCustomInserter = 1; 539 let DisableEncoding = "$dst"; 540 } 541 542 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 543 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 544 def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >; 545 def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >; 546 def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >; 547 def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >; 548 def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >; 549 def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >; 550 def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >; 551 def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >; 552 def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >; 553 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 554 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 555 >; 556 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 557 [(truncstorei8_local i32:$src1, i32:$src0)] 558 >; 559 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 560 [(truncstorei16_local i32:$src1, i32:$src0)] 561 >; 562 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 563 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))] 564 >; 565 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 566 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))] 567 >; 568 def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND", 569 [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))] 570 >; 571 def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR", 572 [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))] 573 >; 574 def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR", 575 [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))] 576 >; 577 def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT", 578 [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))] 579 >; 580 def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT", 581 [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))] 582 >; 583 def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT", 584 [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))] 585 >; 586 def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT", 587 [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))] 588 >; 589 def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG", 590 [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))] 591 >; 592 def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST", 593 [(set i32:$dst, (atomic_cmp_swap_32_local i32:$src0, i32:$src1, i32:$src2))] 594 >; 595 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 596 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))] 597 >; 598 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 599 [(set i32:$dst, (sextloadi8_local i32:$src0))] 600 >; 601 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 602 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 603 >; 604 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 605 [(set i32:$dst, (sextloadi16_local i32:$src0))] 606 >; 607 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 608 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 609 >; 610 611 // TRUNC is used for the FLT_TO_INT instructions to work around a 612 // perceived problem where the rounding modes are applied differently 613 // depending on the instruction and the slot they are in. 614 // See: 615 // https://bugs.freedesktop.org/show_bug.cgi?id=50232 616 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 617 // 618 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 619 // which do not need to be truncated since the fp values are 0.0f or 1.0f. 620 // We should look into handling these cases separately. 621 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 622 623 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 624 625 // SHA-256 Patterns 626 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>; 627 628 def EG_ExportSwz : ExportSwzInst { 629 let Word1{19-16} = 0; // BURST_COUNT 630 let Word1{20} = 0; // VALID_PIXEL_MODE 631 let Word1{21} = eop; 632 let Word1{29-22} = inst; 633 let Word1{30} = 0; // MARK 634 let Word1{31} = 1; // BARRIER 635 } 636 defm : ExportPattern<EG_ExportSwz, 83>; 637 638 def EG_ExportBuf : ExportBufInst { 639 let Word1{19-16} = 0; // BURST_COUNT 640 let Word1{20} = 0; // VALID_PIXEL_MODE 641 let Word1{21} = eop; 642 let Word1{29-22} = inst; 643 let Word1{30} = 0; // MARK 644 let Word1{31} = 1; // BARRIER 645 } 646 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 647 648 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 649 "TEX $COUNT @$ADDR"> { 650 let POP_COUNT = 0; 651 } 652 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 653 "VTX $COUNT @$ADDR"> { 654 let POP_COUNT = 0; 655 } 656 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 657 "LOOP_START_DX10 @$ADDR"> { 658 let POP_COUNT = 0; 659 let COUNT = 0; 660 } 661 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 662 let POP_COUNT = 0; 663 let COUNT = 0; 664 } 665 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 666 "LOOP_BREAK @$ADDR"> { 667 let POP_COUNT = 0; 668 let COUNT = 0; 669 } 670 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 671 "CONTINUE @$ADDR"> { 672 let POP_COUNT = 0; 673 let COUNT = 0; 674 } 675 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 676 "JUMP @$ADDR POP:$POP_COUNT"> { 677 let COUNT = 0; 678 } 679 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 680 "PUSH @$ADDR POP:$POP_COUNT"> { 681 let COUNT = 0; 682 } 683 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 684 "ELSE @$ADDR POP:$POP_COUNT"> { 685 let COUNT = 0; 686 } 687 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 688 let ADDR = 0; 689 let COUNT = 0; 690 let POP_COUNT = 0; 691 } 692 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 693 "POP @$ADDR POP:$POP_COUNT"> { 694 let COUNT = 0; 695 } 696 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 697 let COUNT = 0; 698 let POP_COUNT = 0; 699 let ADDR = 0; 700 let END_OF_PROGRAM = 1; 701 } 702 703 } // End Predicates = [isEGorCayman] 704
