1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // TableGen definitions for instructions which are available on R600 family 11 // GPUs. 12 // 13 //===----------------------------------------------------------------------===// 14 15 include "R600Intrinsics.td" 16 include "R600InstrFormats.td" 17 18 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> : 19 InstR600 <outs, ins, asm, pattern, NullALU> { 20 21 let Namespace = "AMDGPU"; 22 } 23 24 def MEMxi : Operand<iPTR> { 25 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 26 let PrintMethod = "printMemOperand"; 27 } 28 29 def MEMrr : Operand<iPTR> { 30 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 31 } 32 33 // Operands for non-registers 34 35 class InstFlag<string PM = "printOperand", int Default = 0> 36 : OperandWithDefaultOps <i32, (ops (i32 Default))> { 37 let PrintMethod = PM; 38 } 39 40 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers 41 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> { 42 let PrintMethod = "printSel"; 43 } 44 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> { 45 let PrintMethod = "printBankSwizzle"; 46 } 47 48 def LITERAL : InstFlag<"printLiteral">; 49 50 def WRITE : InstFlag <"printWrite", 1>; 51 def OMOD : InstFlag <"printOMOD">; 52 def REL : InstFlag <"printRel">; 53 def CLAMP : InstFlag <"printClamp">; 54 def NEG : InstFlag <"printNeg">; 55 def ABS : InstFlag <"printAbs">; 56 def UEM : InstFlag <"printUpdateExecMask">; 57 def UP : InstFlag <"printUpdatePred">; 58 59 // XXX: The r600g finalizer in Mesa expects last to be one in most cases. 60 // Once we start using the packetizer in this backend we should have this 61 // default to 0. 62 def LAST : InstFlag<"printLast", 1>; 63 def RSel : Operand<i32> { 64 let PrintMethod = "printRSel"; 65 } 66 def CT: Operand<i32> { 67 let PrintMethod = "printCT"; 68 } 69 70 def FRAMEri : Operand<iPTR> { 71 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index); 72 } 73 74 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 75 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 76 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 77 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>; 78 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>; 79 80 81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 82 (ops PRED_SEL_OFF)>; 83 84 85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 86 87 // Class for instructions with only one source register. 88 // If you add new ins to this instruction, make sure they are listed before 89 // $literal, because the backend currently assumes that the last operand is 90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in 91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(), 92 // and R600InstrInfo::getOperandIdx(). 93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern, 94 InstrItinClass itin = AnyALU> : 95 InstR600 <(outs R600_Reg32:$dst), 96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 99 BANK_SWIZZLE:$bank_swizzle), 100 !strconcat(" ", opName, 101 "$clamp $last $dst$write$dst_rel$omod, " 102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 103 "$pred_sel $bank_swizzle"), 104 pattern, 105 itin>, 106 R600ALU_Word0, 107 R600ALU_Word1_OP2 <inst> { 108 109 let src1 = 0; 110 let src1_rel = 0; 111 let src1_neg = 0; 112 let src1_abs = 0; 113 let update_exec_mask = 0; 114 let update_pred = 0; 115 let HasNativeOperands = 1; 116 let Op1 = 1; 117 let ALUInst = 1; 118 let DisableEncoding = "$literal"; 119 let UseNamedOperandTable = 1; 120 121 let Inst{31-0} = Word0; 122 let Inst{63-32} = Word1; 123 } 124 125 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 126 InstrItinClass itin = AnyALU> : 127 R600_1OP <inst, opName, 128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin 129 >; 130 131 // If you add or change the operands for R600_2OP instructions, you must 132 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h, 133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx(). 134 class R600_2OP <bits<11> inst, string opName, list<dag> pattern, 135 InstrItinClass itin = AnyALU> : 136 InstR600 <(outs R600_Reg32:$dst), 137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write, 138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 142 BANK_SWIZZLE:$bank_swizzle), 143 !strconcat(" ", opName, 144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, " 145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, " 147 "$pred_sel $bank_swizzle"), 148 pattern, 149 itin>, 150 R600ALU_Word0, 151 R600ALU_Word1_OP2 <inst> { 152 153 let HasNativeOperands = 1; 154 let Op2 = 1; 155 let ALUInst = 1; 156 let DisableEncoding = "$literal"; 157 let UseNamedOperandTable = 1; 158 159 let Inst{31-0} = Word0; 160 let Inst{63-32} = Word1; 161 } 162 163 class R600_2OP_Helper <bits<11> inst, string opName, 164 SDPatternOperator node = null_frag, 165 InstrItinClass itin = AnyALU> : 166 R600_2OP <inst, opName, 167 [(set R600_Reg32:$dst, (node R600_Reg32:$src0, 168 R600_Reg32:$src1))], itin 169 >; 170 171 // If you add our change the operands for R600_3OP instructions, you must 172 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h, 173 // R600InstrInfo::buildDefaultInstruction(), and 174 // R600InstrInfo::getOperandIdx(). 175 class R600_3OP <bits<5> inst, string opName, list<dag> pattern, 176 InstrItinClass itin = AnyALU> : 177 InstR600 <(outs R600_Reg32:$dst), 178 (ins REL:$dst_rel, CLAMP:$clamp, 179 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel, 180 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 181 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel, 182 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 183 BANK_SWIZZLE:$bank_swizzle), 184 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, " 185 "$src0_neg$src0$src0_rel, " 186 "$src1_neg$src1$src1_rel, " 187 "$src2_neg$src2$src2_rel, " 188 "$pred_sel" 189 "$bank_swizzle"), 190 pattern, 191 itin>, 192 R600ALU_Word0, 193 R600ALU_Word1_OP3<inst>{ 194 195 let HasNativeOperands = 1; 196 let DisableEncoding = "$literal"; 197 let Op3 = 1; 198 let UseNamedOperandTable = 1; 199 let ALUInst = 1; 200 201 let Inst{31-0} = Word0; 202 let Inst{63-32} = Word1; 203 } 204 205 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern, 206 InstrItinClass itin = VecALU> : 207 InstR600 <(outs R600_Reg32:$dst), 208 ins, 209 asm, 210 pattern, 211 itin>; 212 213 214 215 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0 216 217 def TEX_SHADOW : PatLeaf< 218 (imm), 219 [{uint32_t TType = (uint32_t)N->getZExtValue(); 220 return (TType >= 6 && TType <= 8) || TType == 13; 221 }] 222 >; 223 224 def TEX_RECT : PatLeaf< 225 (imm), 226 [{uint32_t TType = (uint32_t)N->getZExtValue(); 227 return TType == 5; 228 }] 229 >; 230 231 def TEX_ARRAY : PatLeaf< 232 (imm), 233 [{uint32_t TType = (uint32_t)N->getZExtValue(); 234 return TType == 9 || TType == 10 || TType == 16; 235 }] 236 >; 237 238 def TEX_SHADOW_ARRAY : PatLeaf< 239 (imm), 240 [{uint32_t TType = (uint32_t)N->getZExtValue(); 241 return TType == 11 || TType == 12 || TType == 17; 242 }] 243 >; 244 245 def TEX_MSAA : PatLeaf< 246 (imm), 247 [{uint32_t TType = (uint32_t)N->getZExtValue(); 248 return TType == 14; 249 }] 250 >; 251 252 def TEX_ARRAY_MSAA : PatLeaf< 253 (imm), 254 [{uint32_t TType = (uint32_t)N->getZExtValue(); 255 return TType == 15; 256 }] 257 >; 258 259 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask, 260 dag outs, dag ins, string asm, list<dag> pattern> : 261 InstR600ISA <outs, ins, asm, pattern>, 262 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { 263 264 let rat_id = ratid; 265 let rat_inst = ratinst; 266 let rim = 0; 267 // XXX: Have a separate instruction for non-indexed writes. 268 let type = 1; 269 let rw_rel = 0; 270 let elem_size = 0; 271 272 let array_size = 0; 273 let comp_mask = mask; 274 let burst_count = 0; 275 let vpm = 0; 276 let cf_inst = cfinst; 277 let mark = 0; 278 let barrier = 1; 279 280 let Inst{31-0} = Word0; 281 let Inst{63-32} = Word1; 282 let IsExport = 1; 283 284 } 285 286 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 287 : InstR600ISA <outs, (ins MEMxi:$src_gpr), !strconcat(" ", name), pattern>, 288 VTX_WORD1_GPR { 289 290 // Static fields 291 let DST_REL = 0; 292 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 293 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 294 // however, based on my testing if USE_CONST_FIELDS is set, then all 295 // these fields need to be set to 0. 296 let USE_CONST_FIELDS = 0; 297 let NUM_FORMAT_ALL = 1; 298 let FORMAT_COMP_ALL = 0; 299 let SRF_MODE_ALL = 0; 300 301 let Inst{63-32} = Word1; 302 // LLVM can only encode 64-bit instructions, so these fields are manually 303 // encoded in R600CodeEmitter 304 // 305 // bits<16> OFFSET; 306 // bits<2> ENDIAN_SWAP = 0; 307 // bits<1> CONST_BUF_NO_STRIDE = 0; 308 // bits<1> MEGA_FETCH = 0; 309 // bits<1> ALT_CONST = 0; 310 // bits<2> BUFFER_INDEX_MODE = 0; 311 312 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 313 // is done in R600CodeEmitter 314 // 315 // Inst{79-64} = OFFSET; 316 // Inst{81-80} = ENDIAN_SWAP; 317 // Inst{82} = CONST_BUF_NO_STRIDE; 318 // Inst{83} = MEGA_FETCH; 319 // Inst{84} = ALT_CONST; 320 // Inst{86-85} = BUFFER_INDEX_MODE; 321 // Inst{95-86} = 0; Reserved 322 323 // VTX_WORD3 (Padding) 324 // 325 // Inst{127-96} = 0; 326 327 let VTXInst = 1; 328 } 329 330 class LoadParamFrag <PatFrag load_type> : PatFrag < 331 (ops node:$ptr), (load_type node:$ptr), 332 [{ return isConstantLoad(cast<LoadSDNode>(N), 0) || 333 (cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS); }] 334 >; 335 336 def load_param : LoadParamFrag<load>; 337 def load_param_exti8 : LoadParamFrag<az_extloadi8>; 338 def load_param_exti16 : LoadParamFrag<az_extloadi16>; 339 340 class LoadVtxId1 <PatFrag load> : PatFrag < 341 (ops node:$ptr), (load node:$ptr), [{ 342 const MemSDNode *LD = cast<MemSDNode>(N); 343 return LD->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS || 344 (LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && 345 !isa<GlobalValue>(GetUnderlyingObject( 346 LD->getMemOperand()->getValue(), CurDAG->getDataLayout()))); 347 }]>; 348 349 def vtx_id1_az_extloadi8 : LoadVtxId1 <az_extloadi8>; 350 def vtx_id1_az_extloadi16 : LoadVtxId1 <az_extloadi16>; 351 def vtx_id1_load : LoadVtxId1 <load>; 352 353 class LoadVtxId2 <PatFrag load> : PatFrag < 354 (ops node:$ptr), (load node:$ptr), [{ 355 const MemSDNode *LD = cast<MemSDNode>(N); 356 return LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && 357 isa<GlobalValue>(GetUnderlyingObject( 358 LD->getMemOperand()->getValue(), CurDAG->getDataLayout())); 359 }]>; 360 361 def vtx_id2_az_extloadi8 : LoadVtxId2 <az_extloadi8>; 362 def vtx_id2_az_extloadi16 : LoadVtxId2 <az_extloadi16>; 363 def vtx_id2_load : LoadVtxId2 <load>; 364 365 def isR600 : Predicate<"Subtarget->getGeneration() <= R600Subtarget::R700">; 366 367 def isR600toCayman 368 : Predicate< 369 "Subtarget->getGeneration() <= R600Subtarget::NORTHERN_ISLANDS">; 370 371 //===----------------------------------------------------------------------===// 372 // R600 SDNodes 373 //===----------------------------------------------------------------------===// 374 375 def INTERP_PAIR_XY : AMDGPUShaderInst < 376 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1), 377 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 378 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1", 379 []>; 380 381 def INTERP_PAIR_ZW : AMDGPUShaderInst < 382 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1), 383 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 384 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1", 385 []>; 386 387 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS", 388 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>, 389 [SDNPVariadic] 390 >; 391 392 def DOT4 : SDNode<"AMDGPUISD::DOT4", 393 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, 394 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>, 395 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>, 396 [] 397 >; 398 399 def COS_HW : SDNode<"AMDGPUISD::COS_HW", 400 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 401 >; 402 403 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW", 404 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 405 >; 406 407 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>; 408 409 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>; 410 411 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> { 412 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, 413 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw), 414 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz), 415 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z), 416 (i32 imm:$DST_SEL_W), 417 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID), 418 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z), 419 (i32 imm:$COORD_TYPE_W)), 420 (inst R600_Reg128:$SRC_GPR, 421 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw, 422 imm:$offsetx, imm:$offsety, imm:$offsetz, 423 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z, 424 imm:$DST_SEL_W, 425 imm:$RESOURCE_ID, imm:$SAMPLER_ID, 426 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z, 427 imm:$COORD_TYPE_W)>; 428 } 429 430 //===----------------------------------------------------------------------===// 431 // Interpolation Instructions 432 //===----------------------------------------------------------------------===// 433 434 def INTERP_VEC_LOAD : AMDGPUShaderInst < 435 (outs R600_Reg128:$dst), 436 (ins i32imm:$src0), 437 "INTERP_LOAD $src0 : $dst">; 438 439 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { 440 let bank_swizzle = 5; 441 } 442 443 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> { 444 let bank_swizzle = 5; 445 } 446 447 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>; 448 449 //===----------------------------------------------------------------------===// 450 // Export Instructions 451 //===----------------------------------------------------------------------===// 452 453 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>; 454 455 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType, 456 [SDNPHasChain, SDNPSideEffect]>; 457 458 class ExportWord0 { 459 field bits<32> Word0; 460 461 bits<13> arraybase; 462 bits<2> type; 463 bits<7> gpr; 464 bits<2> elem_size; 465 466 let Word0{12-0} = arraybase; 467 let Word0{14-13} = type; 468 let Word0{21-15} = gpr; 469 let Word0{22} = 0; // RW_REL 470 let Word0{29-23} = 0; // INDEX_GPR 471 let Word0{31-30} = elem_size; 472 } 473 474 class ExportSwzWord1 { 475 field bits<32> Word1; 476 477 bits<3> sw_x; 478 bits<3> sw_y; 479 bits<3> sw_z; 480 bits<3> sw_w; 481 bits<1> eop; 482 bits<8> inst; 483 484 let Word1{2-0} = sw_x; 485 let Word1{5-3} = sw_y; 486 let Word1{8-6} = sw_z; 487 let Word1{11-9} = sw_w; 488 } 489 490 class ExportBufWord1 { 491 field bits<32> Word1; 492 493 bits<12> arraySize; 494 bits<4> compMask; 495 bits<1> eop; 496 bits<8> inst; 497 498 let Word1{11-0} = arraySize; 499 let Word1{15-12} = compMask; 500 } 501 502 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> { 503 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), 504 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), 505 (ExportInst R600_Reg128:$src, imm:$type, imm:$base, 506 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0) 507 >; 508 509 } 510 511 multiclass SteamOutputExportPattern<Instruction ExportInst, 512 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> { 513 // Stream0 514 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 515 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)), 516 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 517 4095, imm:$mask, buf0inst, 0)>; 518 // Stream1 519 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 520 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)), 521 (ExportInst $src, 0, imm:$arraybase, 522 4095, imm:$mask, buf1inst, 0)>; 523 // Stream2 524 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 525 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)), 526 (ExportInst $src, 0, imm:$arraybase, 527 4095, imm:$mask, buf2inst, 0)>; 528 // Stream3 529 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 530 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)), 531 (ExportInst $src, 0, imm:$arraybase, 532 4095, imm:$mask, buf3inst, 0)>; 533 } 534 535 // Export Instructions should not be duplicated by TailDuplication pass 536 // (which assumes that duplicable instruction are affected by exec mask) 537 let usesCustomInserter = 1, isNotDuplicable = 1 in { 538 539 class ExportSwzInst : InstR600ISA<( 540 outs), 541 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 542 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst, 543 i32imm:$eop), 544 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"), 545 []>, ExportWord0, ExportSwzWord1 { 546 let elem_size = 3; 547 let Inst{31-0} = Word0; 548 let Inst{63-32} = Word1; 549 let IsExport = 1; 550 } 551 552 } // End usesCustomInserter = 1 553 554 class ExportBufInst : InstR600ISA<( 555 outs), 556 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 557 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop), 558 !strconcat("EXPORT", " $gpr"), 559 []>, ExportWord0, ExportBufWord1 { 560 let elem_size = 0; 561 let Inst{31-0} = Word0; 562 let Inst{63-32} = Word1; 563 let IsExport = 1; 564 } 565 566 //===----------------------------------------------------------------------===// 567 // Control Flow Instructions 568 //===----------------------------------------------------------------------===// 569 570 571 def KCACHE : InstFlag<"printKCache">; 572 573 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs), 574 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, 575 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1, 576 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, 577 i32imm:$COUNT, i32imm:$Enabled), 578 !strconcat(OpName, " $COUNT, @$ADDR, " 579 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"), 580 [] >, CF_ALU_WORD0, CF_ALU_WORD1 { 581 field bits<64> Inst; 582 583 let CF_INST = inst; 584 let ALT_CONST = 0; 585 let WHOLE_QUAD_MODE = 0; 586 let BARRIER = 1; 587 let isCodeGenOnly = 1; 588 let UseNamedOperandTable = 1; 589 590 let Inst{31-0} = Word0; 591 let Inst{63-32} = Word1; 592 } 593 594 class CF_WORD0_R600 { 595 field bits<32> Word0; 596 597 bits<32> ADDR; 598 599 let Word0 = ADDR; 600 } 601 602 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), 603 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 { 604 field bits<64> Inst; 605 bits<4> CNT; 606 607 let CF_INST = inst; 608 let BARRIER = 1; 609 let CF_CONST = 0; 610 let VALID_PIXEL_MODE = 0; 611 let COND = 0; 612 let COUNT = CNT{2-0}; 613 let CALL_COUNT = 0; 614 let COUNT_3 = CNT{3}; 615 let END_OF_PROGRAM = 0; 616 let WHOLE_QUAD_MODE = 0; 617 618 let Inst{31-0} = Word0; 619 let Inst{63-32} = Word1; 620 } 621 622 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), 623 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG { 624 field bits<64> Inst; 625 626 let CF_INST = inst; 627 let BARRIER = 1; 628 let JUMPTABLE_SEL = 0; 629 let CF_CONST = 0; 630 let VALID_PIXEL_MODE = 0; 631 let COND = 0; 632 let END_OF_PROGRAM = 0; 633 634 let Inst{31-0} = Word0; 635 let Inst{63-32} = Word1; 636 } 637 638 def CF_ALU : ALU_CLAUSE<8, "ALU">; 639 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">; 640 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">; 641 def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">; 642 def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">; 643 def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">; 644 645 def FETCH_CLAUSE : AMDGPUInst <(outs), 646 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > { 647 field bits<8> Inst; 648 bits<8> num; 649 let Inst = num; 650 let isCodeGenOnly = 1; 651 } 652 653 def ALU_CLAUSE : AMDGPUInst <(outs), 654 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > { 655 field bits<8> Inst; 656 bits<8> num; 657 let Inst = num; 658 let isCodeGenOnly = 1; 659 } 660 661 def LITERALS : AMDGPUInst <(outs), 662 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > { 663 let isCodeGenOnly = 1; 664 665 field bits<64> Inst; 666 bits<32> literal1; 667 bits<32> literal2; 668 669 let Inst{31-0} = literal1; 670 let Inst{63-32} = literal2; 671 } 672 673 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > { 674 field bits<64> Inst; 675 } 676 677 let Predicates = [isR600toCayman] in { 678 679 //===----------------------------------------------------------------------===// 680 // Common Instructions R600, R700, Evergreen, Cayman 681 //===----------------------------------------------------------------------===// 682 683 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>; 684 // Non-IEEE MUL: 0 * anything = 0 685 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE">; 686 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>; 687 // TODO: Do these actually match the regular fmin/fmax behavior? 688 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>; 689 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>; 690 // According to https://msdn.microsoft.com/en-us/library/windows/desktop/cc308050%28v=vs.85%29.aspx 691 // DX10 min/max returns the other operand if one is NaN, 692 // this matches http://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic 693 def MAX_DX10 : R600_2OP_Helper <0x5, "MAX_DX10", fmaxnum>; 694 def MIN_DX10 : R600_2OP_Helper <0x6, "MIN_DX10", fminnum>; 695 696 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 697 // so some of the instruction names don't match the asm string. 698 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 699 def SETE : R600_2OP < 700 0x08, "SETE", 701 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))] 702 >; 703 704 def SGT : R600_2OP < 705 0x09, "SETGT", 706 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))] 707 >; 708 709 def SGE : R600_2OP < 710 0xA, "SETGE", 711 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))] 712 >; 713 714 def SNE : R600_2OP < 715 0xB, "SETNE", 716 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))] 717 >; 718 719 def SETE_DX10 : R600_2OP < 720 0xC, "SETE_DX10", 721 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))] 722 >; 723 724 def SETGT_DX10 : R600_2OP < 725 0xD, "SETGT_DX10", 726 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))] 727 >; 728 729 def SETGE_DX10 : R600_2OP < 730 0xE, "SETGE_DX10", 731 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))] 732 >; 733 734 // FIXME: This should probably be COND_ONE 735 def SETNE_DX10 : R600_2OP < 736 0xF, "SETNE_DX10", 737 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))] 738 >; 739 740 // FIXME: Need combine for AMDGPUfract 741 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>; 742 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>; 743 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>; 744 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>; 745 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>; 746 747 def MOV : R600_1OP <0x19, "MOV", []>; 748 749 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { 750 751 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst < 752 (outs R600_Reg32:$dst), 753 (ins immType:$imm), 754 "", 755 [] 756 >; 757 758 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 759 760 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 761 def : Pat < 762 (imm:$val), 763 (MOV_IMM_I32 imm:$val) 764 >; 765 766 def MOV_IMM_GLOBAL_ADDR : MOV_IMM<iPTR, i32imm>; 767 def : Pat < 768 (AMDGPUconstdata_ptr tglobaladdr:$addr), 769 (MOV_IMM_GLOBAL_ADDR tglobaladdr:$addr) 770 >; 771 772 773 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 774 def : Pat < 775 (fpimm:$val), 776 (MOV_IMM_F32 fpimm:$val) 777 >; 778 779 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>; 780 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>; 781 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>; 782 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>; 783 784 let hasSideEffects = 1 in { 785 786 def KILLGT : R600_2OP <0x2D, "KILLGT", []>; 787 788 } // end hasSideEffects 789 790 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>; 791 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>; 792 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>; 793 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>; 794 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>; 795 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>; 796 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", smax>; 797 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", smin>; 798 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", umax>; 799 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", umin>; 800 801 def SETE_INT : R600_2OP < 802 0x3A, "SETE_INT", 803 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))] 804 >; 805 806 def SETGT_INT : R600_2OP < 807 0x3B, "SETGT_INT", 808 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))] 809 >; 810 811 def SETGE_INT : R600_2OP < 812 0x3C, "SETGE_INT", 813 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))] 814 >; 815 816 def SETNE_INT : R600_2OP < 817 0x3D, "SETNE_INT", 818 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))] 819 >; 820 821 def SETGT_UINT : R600_2OP < 822 0x3E, "SETGT_UINT", 823 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))] 824 >; 825 826 def SETGE_UINT : R600_2OP < 827 0x3F, "SETGE_UINT", 828 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))] 829 >; 830 831 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>; 832 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>; 833 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>; 834 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>; 835 836 def CNDE_INT : R600_3OP < 837 0x1C, "CNDE_INT", 838 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))] 839 >; 840 841 def CNDGE_INT : R600_3OP < 842 0x1E, "CNDGE_INT", 843 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))] 844 >; 845 846 def CNDGT_INT : R600_3OP < 847 0x1D, "CNDGT_INT", 848 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))] 849 >; 850 851 //===----------------------------------------------------------------------===// 852 // Texture instructions 853 //===----------------------------------------------------------------------===// 854 855 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 856 857 class R600_TEX <bits<11> inst, string opName> : 858 InstR600 <(outs R600_Reg128:$DST_GPR), 859 (ins R600_Reg128:$SRC_GPR, 860 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw, 861 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz, 862 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W, 863 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, 864 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z, 865 CT:$COORD_TYPE_W), 866 !strconcat(" ", opName, 867 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, " 868 "$SRC_GPR.$srcx$srcy$srcz$srcw " 869 "RID:$RESOURCE_ID SID:$SAMPLER_ID " 870 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"), 871 [], 872 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 { 873 let Inst{31-0} = Word0; 874 let Inst{63-32} = Word1; 875 876 let TEX_INST = inst{4-0}; 877 let SRC_REL = 0; 878 let DST_REL = 0; 879 let LOD_BIAS = 0; 880 881 let INST_MOD = 0; 882 let FETCH_WHOLE_QUAD = 0; 883 let ALT_CONST = 0; 884 let SAMPLER_INDEX_MODE = 0; 885 let RESOURCE_INDEX_MODE = 0; 886 887 let TEXInst = 1; 888 } 889 890 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 891 892 893 894 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">; 895 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">; 896 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">; 897 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">; 898 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">; 899 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">; 900 def TEX_LD : R600_TEX <0x03, "TEX_LD">; 901 def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> { 902 let INST_MOD = 1; 903 } 904 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">; 905 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">; 906 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">; 907 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">; 908 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">; 909 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">; 910 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">; 911 912 defm : TexPattern<0, TEX_SAMPLE>; 913 defm : TexPattern<1, TEX_SAMPLE_C>; 914 defm : TexPattern<2, TEX_SAMPLE_L>; 915 defm : TexPattern<3, TEX_SAMPLE_C_L>; 916 defm : TexPattern<4, TEX_SAMPLE_LB>; 917 defm : TexPattern<5, TEX_SAMPLE_C_LB>; 918 defm : TexPattern<6, TEX_LD, v4i32>; 919 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>; 920 defm : TexPattern<8, TEX_GET_GRADIENTS_H>; 921 defm : TexPattern<9, TEX_GET_GRADIENTS_V>; 922 defm : TexPattern<10, TEX_LDPTR, v4i32>; 923 924 //===----------------------------------------------------------------------===// 925 // Helper classes for common instructions 926 //===----------------------------------------------------------------------===// 927 928 class MUL_LIT_Common <bits<5> inst> : R600_3OP < 929 inst, "MUL_LIT", 930 [] 931 >; 932 933 class MULADD_Common <bits<5> inst> : R600_3OP < 934 inst, "MULADD", 935 [] 936 >; 937 938 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP < 939 inst, "MULADD_IEEE", 940 [(set f32:$dst, (fmad f32:$src0, f32:$src1, f32:$src2))] 941 >; 942 943 class FMA_Common <bits<5> inst> : R600_3OP < 944 inst, "FMA", 945 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU 946 >; 947 948 class CNDE_Common <bits<5> inst> : R600_3OP < 949 inst, "CNDE", 950 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))] 951 >; 952 953 class CNDGT_Common <bits<5> inst> : R600_3OP < 954 inst, "CNDGT", 955 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))] 956 > { 957 let Itinerary = VecALU; 958 } 959 960 class CNDGE_Common <bits<5> inst> : R600_3OP < 961 inst, "CNDGE", 962 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))] 963 > { 964 let Itinerary = VecALU; 965 } 966 967 968 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in { 969 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins 970 // Slot X 971 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X, 972 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X, 973 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X, 974 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X, 975 R600_Pred:$pred_sel_X, 976 // Slot Y 977 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y, 978 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y, 979 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y, 980 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y, 981 R600_Pred:$pred_sel_Y, 982 // Slot Z 983 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z, 984 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z, 985 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z, 986 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z, 987 R600_Pred:$pred_sel_Z, 988 // Slot W 989 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W, 990 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W, 991 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W, 992 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W, 993 R600_Pred:$pred_sel_W, 994 LITERAL:$literal0, LITERAL:$literal1), 995 "", 996 pattern, 997 AnyALU> { 998 999 let UseNamedOperandTable = 1; 1000 1001 } 1002 } 1003 1004 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4 1005 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X, 1006 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y, 1007 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z, 1008 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>; 1009 1010 1011 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>; 1012 1013 1014 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 1015 multiclass CUBE_Common <bits<11> inst> { 1016 1017 def _pseudo : InstR600 < 1018 (outs R600_Reg128:$dst), 1019 (ins R600_Reg128:$src0), 1020 "CUBE $dst $src0", 1021 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))], 1022 VecALU 1023 > { 1024 let isPseudo = 1; 1025 let UseNamedOperandTable = 1; 1026 } 1027 1028 def _real : R600_2OP <inst, "CUBE", []>; 1029 } 1030 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 1031 1032 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1033 inst, "EXP_IEEE", fexp2 1034 > { 1035 let Itinerary = TransALU; 1036 } 1037 1038 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper < 1039 inst, "FLT_TO_INT", fp_to_sint 1040 > { 1041 let Itinerary = TransALU; 1042 } 1043 1044 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1045 inst, "INT_TO_FLT", sint_to_fp 1046 > { 1047 let Itinerary = TransALU; 1048 } 1049 1050 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1051 inst, "FLT_TO_UINT", fp_to_uint 1052 > { 1053 let Itinerary = TransALU; 1054 } 1055 1056 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1057 inst, "UINT_TO_FLT", uint_to_fp 1058 > { 1059 let Itinerary = TransALU; 1060 } 1061 1062 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP < 1063 inst, "LOG_CLAMPED", [] 1064 >; 1065 1066 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1067 inst, "LOG_IEEE", flog2 1068 > { 1069 let Itinerary = TransALU; 1070 } 1071 1072 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>; 1073 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>; 1074 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>; 1075 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper < 1076 inst, "MULHI_INT", mulhs 1077 > { 1078 let Itinerary = TransALU; 1079 } 1080 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper < 1081 inst, "MULHI", mulhu 1082 > { 1083 let Itinerary = TransALU; 1084 } 1085 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper < 1086 inst, "MULLO_INT", mul 1087 > { 1088 let Itinerary = TransALU; 1089 } 1090 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> { 1091 let Itinerary = TransALU; 1092 } 1093 1094 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP < 1095 inst, "RECIP_CLAMPED", [] 1096 > { 1097 let Itinerary = TransALU; 1098 } 1099 1100 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP < 1101 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))] 1102 > { 1103 let Itinerary = TransALU; 1104 } 1105 1106 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1107 inst, "RECIP_UINT", AMDGPUurecip 1108 > { 1109 let Itinerary = TransALU; 1110 } 1111 1112 // Clamped to maximum. 1113 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper < 1114 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamp 1115 > { 1116 let Itinerary = TransALU; 1117 } 1118 1119 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1120 inst, "RECIPSQRT_IEEE", AMDGPUrsq_legacy 1121 > { 1122 let Itinerary = TransALU; 1123 } 1124 1125 // TODO: There is also RECIPSQRT_FF which clamps to zero. 1126 1127 class SIN_Common <bits<11> inst> : R600_1OP < 1128 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{ 1129 let Trig = 1; 1130 let Itinerary = TransALU; 1131 } 1132 1133 class COS_Common <bits<11> inst> : R600_1OP < 1134 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> { 1135 let Trig = 1; 1136 let Itinerary = TransALU; 1137 } 1138 1139 def CLAMP_R600 : CLAMP <R600_Reg32>; 1140 def FABS_R600 : FABS<R600_Reg32>; 1141 def FNEG_R600 : FNEG<R600_Reg32>; 1142 1143 //===----------------------------------------------------------------------===// 1144 // Helper patterns for complex intrinsics 1145 //===----------------------------------------------------------------------===// 1146 1147 // FIXME: Should be predicated on unsafe fp math. 1148 multiclass DIV_Common <InstR600 recip_ieee> { 1149 def : Pat< 1150 (fdiv f32:$src0, f32:$src1), 1151 (MUL_IEEE $src0, (recip_ieee $src1)) 1152 >; 1153 1154 def : RcpPat<recip_ieee, f32>; 1155 } 1156 1157 //===----------------------------------------------------------------------===// 1158 // R600 / R700 Instructions 1159 //===----------------------------------------------------------------------===// 1160 1161 let Predicates = [isR600] in { 1162 1163 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 1164 def MULADD_r600 : MULADD_Common<0x10>; 1165 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>; 1166 def CNDE_r600 : CNDE_Common<0x18>; 1167 def CNDGT_r600 : CNDGT_Common<0x19>; 1168 def CNDGE_r600 : CNDGE_Common<0x1A>; 1169 def DOT4_r600 : DOT4_Common<0x50>; 1170 defm CUBE_r600 : CUBE_Common<0x52>; 1171 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 1172 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 1173 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 1174 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 1175 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 1176 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 1177 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 1178 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 1179 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 1180 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 1181 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 1182 def SIN_r600 : SIN_Common<0x6E>; 1183 def COS_r600 : COS_Common<0x6F>; 1184 def ASHR_r600 : ASHR_Common<0x70>; 1185 def LSHR_r600 : LSHR_Common<0x71>; 1186 def LSHL_r600 : LSHL_Common<0x72>; 1187 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 1188 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 1189 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 1190 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 1191 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 1192 1193 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 1194 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>; 1195 1196 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; 1197 def : RsqPat<RECIPSQRT_IEEE_r600, f32>; 1198 1199 def R600_ExportSwz : ExportSwzInst { 1200 let Word1{20-17} = 0; // BURST_COUNT 1201 let Word1{21} = eop; 1202 let Word1{22} = 0; // VALID_PIXEL_MODE 1203 let Word1{30-23} = inst; 1204 let Word1{31} = 1; // BARRIER 1205 } 1206 defm : ExportPattern<R600_ExportSwz, 39>; 1207 1208 def R600_ExportBuf : ExportBufInst { 1209 let Word1{20-17} = 0; // BURST_COUNT 1210 let Word1{21} = eop; 1211 let Word1{22} = 0; // VALID_PIXEL_MODE 1212 let Word1{30-23} = inst; 1213 let Word1{31} = 1; // BARRIER 1214 } 1215 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>; 1216 1217 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT), 1218 "TEX $CNT @$ADDR"> { 1219 let POP_COUNT = 0; 1220 } 1221 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT), 1222 "VTX $CNT @$ADDR"> { 1223 let POP_COUNT = 0; 1224 } 1225 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR), 1226 "LOOP_START_DX10 @$ADDR"> { 1227 let POP_COUNT = 0; 1228 let CNT = 0; 1229 } 1230 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 1231 let POP_COUNT = 0; 1232 let CNT = 0; 1233 } 1234 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR), 1235 "LOOP_BREAK @$ADDR"> { 1236 let POP_COUNT = 0; 1237 let CNT = 0; 1238 } 1239 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR), 1240 "CONTINUE @$ADDR"> { 1241 let POP_COUNT = 0; 1242 let CNT = 0; 1243 } 1244 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1245 "JUMP @$ADDR POP:$POP_COUNT"> { 1246 let CNT = 0; 1247 } 1248 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR), 1249 "PUSH_ELSE @$ADDR"> { 1250 let CNT = 0; 1251 let POP_COUNT = 0; // FIXME? 1252 } 1253 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1254 "ELSE @$ADDR POP:$POP_COUNT"> { 1255 let CNT = 0; 1256 } 1257 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> { 1258 let ADDR = 0; 1259 let CNT = 0; 1260 let POP_COUNT = 0; 1261 } 1262 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1263 "POP @$ADDR POP:$POP_COUNT"> { 1264 let CNT = 0; 1265 } 1266 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> { 1267 let CNT = 0; 1268 let POP_COUNT = 0; 1269 let ADDR = 0; 1270 let END_OF_PROGRAM = 1; 1271 } 1272 1273 } 1274 1275 1276 //===----------------------------------------------------------------------===// 1277 // Regist loads and stores - for indirect addressing 1278 //===----------------------------------------------------------------------===// 1279 1280 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>; 1281 1282 1283 //===----------------------------------------------------------------------===// 1284 // Pseudo instructions 1285 //===----------------------------------------------------------------------===// 1286 1287 let isPseudo = 1 in { 1288 1289 def PRED_X : InstR600 < 1290 (outs R600_Predicate_Bit:$dst), 1291 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), 1292 "", [], NullALU> { 1293 let FlagOperandIdx = 3; 1294 } 1295 1296 let isTerminator = 1, isBranch = 1 in { 1297 def JUMP_COND : InstR600 < 1298 (outs), 1299 (ins brtarget:$target, R600_Predicate_Bit:$p), 1300 "JUMP $target ($p)", 1301 [], AnyALU 1302 >; 1303 1304 def JUMP : InstR600 < 1305 (outs), 1306 (ins brtarget:$target), 1307 "JUMP $target", 1308 [], AnyALU 1309 > 1310 { 1311 let isPredicable = 1; 1312 let isBarrier = 1; 1313 } 1314 1315 } // End isTerminator = 1, isBranch = 1 1316 1317 let usesCustomInserter = 1 in { 1318 1319 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in { 1320 1321 def MASK_WRITE : AMDGPUShaderInst < 1322 (outs), 1323 (ins R600_Reg32:$src), 1324 "MASK_WRITE $src", 1325 [] 1326 >; 1327 1328 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1 1329 1330 1331 def TXD: InstR600 < 1332 (outs R600_Reg128:$dst), 1333 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1334 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1335 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [], 1336 NullALU > { 1337 let TEXInst = 1; 1338 } 1339 1340 def TXD_SHADOW: InstR600 < 1341 (outs R600_Reg128:$dst), 1342 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1343 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1344 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1345 [], NullALU> { 1346 let TEXInst = 1; 1347 } 1348 } // End isPseudo = 1 1349 } // End usesCustomInserter = 1 1350 1351 1352 //===----------------------------------------------------------------------===// 1353 // Constant Buffer Addressing Support 1354 //===----------------------------------------------------------------------===// 1355 1356 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in { 1357 def CONST_COPY : Instruction { 1358 let OutOperandList = (outs R600_Reg32:$dst); 1359 let InOperandList = (ins i32imm:$src); 1360 let Pattern = 1361 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))]; 1362 let AsmString = "CONST_COPY"; 1363 let hasSideEffects = 0; 1364 let isAsCheapAsAMove = 1; 1365 let Itinerary = NullALU; 1366 } 1367 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" 1368 1369 def TEX_VTX_CONSTBUF : 1370 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr", 1371 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>, 1372 VTX_WORD1_GPR, VTX_WORD0_eg { 1373 1374 let VC_INST = 0; 1375 let FETCH_TYPE = 2; 1376 let FETCH_WHOLE_QUAD = 0; 1377 let SRC_REL = 0; 1378 let SRC_SEL_X = 0; 1379 let DST_REL = 0; 1380 let USE_CONST_FIELDS = 0; 1381 let NUM_FORMAT_ALL = 2; 1382 let FORMAT_COMP_ALL = 1; 1383 let SRF_MODE_ALL = 1; 1384 let MEGA_FETCH_COUNT = 16; 1385 let DST_SEL_X = 0; 1386 let DST_SEL_Y = 1; 1387 let DST_SEL_Z = 2; 1388 let DST_SEL_W = 3; 1389 let DATA_FORMAT = 35; 1390 1391 let Inst{31-0} = Word0; 1392 let Inst{63-32} = Word1; 1393 1394 // LLVM can only encode 64-bit instructions, so these fields are manually 1395 // encoded in R600CodeEmitter 1396 // 1397 // bits<16> OFFSET; 1398 // bits<2> ENDIAN_SWAP = 0; 1399 // bits<1> CONST_BUF_NO_STRIDE = 0; 1400 // bits<1> MEGA_FETCH = 0; 1401 // bits<1> ALT_CONST = 0; 1402 // bits<2> BUFFER_INDEX_MODE = 0; 1403 1404 1405 1406 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1407 // is done in R600CodeEmitter 1408 // 1409 // Inst{79-64} = OFFSET; 1410 // Inst{81-80} = ENDIAN_SWAP; 1411 // Inst{82} = CONST_BUF_NO_STRIDE; 1412 // Inst{83} = MEGA_FETCH; 1413 // Inst{84} = ALT_CONST; 1414 // Inst{86-85} = BUFFER_INDEX_MODE; 1415 // Inst{95-86} = 0; Reserved 1416 1417 // VTX_WORD3 (Padding) 1418 // 1419 // Inst{127-96} = 0; 1420 let VTXInst = 1; 1421 } 1422 1423 def TEX_VTX_TEXBUF: 1424 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr">, 1425 VTX_WORD1_GPR, VTX_WORD0_eg { 1426 1427 let VC_INST = 0; 1428 let FETCH_TYPE = 2; 1429 let FETCH_WHOLE_QUAD = 0; 1430 let SRC_REL = 0; 1431 let SRC_SEL_X = 0; 1432 let DST_REL = 0; 1433 let USE_CONST_FIELDS = 1; 1434 let NUM_FORMAT_ALL = 0; 1435 let FORMAT_COMP_ALL = 0; 1436 let SRF_MODE_ALL = 1; 1437 let MEGA_FETCH_COUNT = 16; 1438 let DST_SEL_X = 0; 1439 let DST_SEL_Y = 1; 1440 let DST_SEL_Z = 2; 1441 let DST_SEL_W = 3; 1442 let DATA_FORMAT = 0; 1443 1444 let Inst{31-0} = Word0; 1445 let Inst{63-32} = Word1; 1446 1447 // LLVM can only encode 64-bit instructions, so these fields are manually 1448 // encoded in R600CodeEmitter 1449 // 1450 // bits<16> OFFSET; 1451 // bits<2> ENDIAN_SWAP = 0; 1452 // bits<1> CONST_BUF_NO_STRIDE = 0; 1453 // bits<1> MEGA_FETCH = 0; 1454 // bits<1> ALT_CONST = 0; 1455 // bits<2> BUFFER_INDEX_MODE = 0; 1456 1457 1458 1459 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1460 // is done in R600CodeEmitter 1461 // 1462 // Inst{79-64} = OFFSET; 1463 // Inst{81-80} = ENDIAN_SWAP; 1464 // Inst{82} = CONST_BUF_NO_STRIDE; 1465 // Inst{83} = MEGA_FETCH; 1466 // Inst{84} = ALT_CONST; 1467 // Inst{86-85} = BUFFER_INDEX_MODE; 1468 // Inst{95-86} = 0; Reserved 1469 1470 // VTX_WORD3 (Padding) 1471 // 1472 // Inst{127-96} = 0; 1473 let VTXInst = 1; 1474 } 1475 1476 //===---------------------------------------------------------------------===// 1477 // Flow and Program control Instructions 1478 //===---------------------------------------------------------------------===// 1479 class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern> 1480 : Instruction { 1481 1482 let Namespace = "AMDGPU"; 1483 dag OutOperandList = outs; 1484 dag InOperandList = ins; 1485 let Pattern = pattern; 1486 let AsmString = !strconcat(asmstr, "\n"); 1487 let isPseudo = 1; 1488 let Itinerary = NullALU; 1489 bit hasIEEEFlag = 0; 1490 bit hasZeroOpFlag = 0; 1491 let mayLoad = 0; 1492 let mayStore = 0; 1493 let hasSideEffects = 0; 1494 let isCodeGenOnly = 1; 1495 } 1496 1497 multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> { 1498 def _i32 : ILFormat<(outs), 1499 (ins brtarget:$target, rci:$src0), 1500 "; i32 Pseudo branch instruction", 1501 [(Op bb:$target, (i32 rci:$src0))]>; 1502 def _f32 : ILFormat<(outs), 1503 (ins brtarget:$target, rcf:$src0), 1504 "; f32 Pseudo branch instruction", 1505 [(Op bb:$target, (f32 rcf:$src0))]>; 1506 } 1507 1508 // Only scalar types should generate flow control 1509 multiclass BranchInstr<string name> { 1510 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src), 1511 !strconcat(name, " $src"), []>; 1512 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src), 1513 !strconcat(name, " $src"), []>; 1514 } 1515 // Only scalar types should generate flow control 1516 multiclass BranchInstr2<string name> { 1517 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1518 !strconcat(name, " $src0, $src1"), []>; 1519 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1520 !strconcat(name, " $src0, $src1"), []>; 1521 } 1522 1523 //===---------------------------------------------------------------------===// 1524 // Custom Inserter for Branches and returns, this eventually will be a 1525 // separate pass 1526 //===---------------------------------------------------------------------===// 1527 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in { 1528 def BRANCH : ILFormat<(outs), (ins brtarget:$target), 1529 "; Pseudo unconditional branch instruction", 1530 [(br bb:$target)]>; 1531 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>; 1532 } 1533 1534 //===---------------------------------------------------------------------===// 1535 // Return instruction 1536 //===---------------------------------------------------------------------===// 1537 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1, 1538 usesCustomInserter = 1 in { 1539 def RETURN : ILFormat<(outs), (ins variable_ops), 1540 "RETURN", [(AMDGPUendpgm)] 1541 >; 1542 } 1543 1544 //===----------------------------------------------------------------------===// 1545 // Branch Instructions 1546 //===----------------------------------------------------------------------===// 1547 1548 def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src), 1549 "IF_PREDICATE_SET $src", []>; 1550 1551 let isTerminator=1 in { 1552 def BREAK : ILFormat< (outs), (ins), 1553 "BREAK", []>; 1554 def CONTINUE : ILFormat< (outs), (ins), 1555 "CONTINUE", []>; 1556 def DEFAULT : ILFormat< (outs), (ins), 1557 "DEFAULT", []>; 1558 def ELSE : ILFormat< (outs), (ins), 1559 "ELSE", []>; 1560 def ENDSWITCH : ILFormat< (outs), (ins), 1561 "ENDSWITCH", []>; 1562 def ENDMAIN : ILFormat< (outs), (ins), 1563 "ENDMAIN", []>; 1564 def END : ILFormat< (outs), (ins), 1565 "END", []>; 1566 def ENDFUNC : ILFormat< (outs), (ins), 1567 "ENDFUNC", []>; 1568 def ENDIF : ILFormat< (outs), (ins), 1569 "ENDIF", []>; 1570 def WHILELOOP : ILFormat< (outs), (ins), 1571 "WHILE", []>; 1572 def ENDLOOP : ILFormat< (outs), (ins), 1573 "ENDLOOP", []>; 1574 def FUNC : ILFormat< (outs), (ins), 1575 "FUNC", []>; 1576 def RETDYN : ILFormat< (outs), (ins), 1577 "RET_DYN", []>; 1578 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1579 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">; 1580 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1581 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">; 1582 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1583 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">; 1584 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1585 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">; 1586 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1587 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">; 1588 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1589 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">; 1590 defm IFC : BranchInstr2<"IFC">; 1591 defm BREAKC : BranchInstr2<"BREAKC">; 1592 defm CONTINUEC : BranchInstr2<"CONTINUEC">; 1593 } 1594 1595 //===----------------------------------------------------------------------===// 1596 // Indirect addressing pseudo instructions 1597 //===----------------------------------------------------------------------===// 1598 1599 let isPseudo = 1 in { 1600 1601 class ExtractVertical <RegisterClass vec_rc> : InstR600 < 1602 (outs R600_Reg32:$dst), 1603 (ins vec_rc:$vec, R600_Reg32:$index), "", 1604 [], 1605 AnyALU 1606 >; 1607 1608 let Constraints = "$dst = $vec" in { 1609 1610 class InsertVertical <RegisterClass vec_rc> : InstR600 < 1611 (outs vec_rc:$dst), 1612 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "", 1613 [], 1614 AnyALU 1615 >; 1616 1617 } // End Constraints = "$dst = $vec" 1618 1619 } // End isPseudo = 1 1620 1621 def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>; 1622 def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>; 1623 1624 def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>; 1625 def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>; 1626 1627 class ExtractVerticalPat <Instruction inst, ValueType vec_ty, 1628 ValueType scalar_ty> : Pat < 1629 (scalar_ty (extractelt vec_ty:$vec, i32:$index)), 1630 (inst $vec, $index) 1631 >; 1632 1633 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>; 1634 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>; 1635 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>; 1636 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>; 1637 1638 class InsertVerticalPat <Instruction inst, ValueType vec_ty, 1639 ValueType scalar_ty> : Pat < 1640 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)), 1641 (inst $vec, $value, $index) 1642 >; 1643 1644 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>; 1645 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>; 1646 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>; 1647 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>; 1648 1649 //===----------------------------------------------------------------------===// 1650 // ISel Patterns 1651 //===----------------------------------------------------------------------===// 1652 1653 // CND*_INT Patterns for f32 True / False values 1654 1655 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat < 1656 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc), 1657 (cnd $src0, $src1, $src2) 1658 >; 1659 1660 def : CND_INT_f32 <CNDE_INT, SETEQ>; 1661 def : CND_INT_f32 <CNDGT_INT, SETGT>; 1662 def : CND_INT_f32 <CNDGE_INT, SETGE>; 1663 1664 //CNDGE_INT extra pattern 1665 def : Pat < 1666 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT), 1667 (CNDGE_INT $src0, $src1, $src2) 1668 >; 1669 1670 // KIL Patterns 1671 def KILP : Pat < 1672 (int_AMDGPU_kilp), 1673 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) 1674 >; 1675 1676 def KIL : Pat < 1677 (int_AMDGPU_kill f32:$src0), 1678 (MASK_WRITE (KILLGT (f32 ZERO), $src0)) 1679 >; 1680 1681 def : Extract_Element <f32, v4f32, 0, sub0>; 1682 def : Extract_Element <f32, v4f32, 1, sub1>; 1683 def : Extract_Element <f32, v4f32, 2, sub2>; 1684 def : Extract_Element <f32, v4f32, 3, sub3>; 1685 1686 def : Insert_Element <f32, v4f32, 0, sub0>; 1687 def : Insert_Element <f32, v4f32, 1, sub1>; 1688 def : Insert_Element <f32, v4f32, 2, sub2>; 1689 def : Insert_Element <f32, v4f32, 3, sub3>; 1690 1691 def : Extract_Element <i32, v4i32, 0, sub0>; 1692 def : Extract_Element <i32, v4i32, 1, sub1>; 1693 def : Extract_Element <i32, v4i32, 2, sub2>; 1694 def : Extract_Element <i32, v4i32, 3, sub3>; 1695 1696 def : Insert_Element <i32, v4i32, 0, sub0>; 1697 def : Insert_Element <i32, v4i32, 1, sub1>; 1698 def : Insert_Element <i32, v4i32, 2, sub2>; 1699 def : Insert_Element <i32, v4i32, 3, sub3>; 1700 1701 def : Extract_Element <f32, v2f32, 0, sub0>; 1702 def : Extract_Element <f32, v2f32, 1, sub1>; 1703 1704 def : Insert_Element <f32, v2f32, 0, sub0>; 1705 def : Insert_Element <f32, v2f32, 1, sub1>; 1706 1707 def : Extract_Element <i32, v2i32, 0, sub0>; 1708 def : Extract_Element <i32, v2i32, 1, sub1>; 1709 1710 def : Insert_Element <i32, v2i32, 0, sub0>; 1711 def : Insert_Element <i32, v2i32, 1, sub1>; 1712 1713 // bitconvert patterns 1714 1715 def : BitConvert <i32, f32, R600_Reg32>; 1716 def : BitConvert <f32, i32, R600_Reg32>; 1717 def : BitConvert <v2f32, v2i32, R600_Reg64>; 1718 def : BitConvert <v2i32, v2f32, R600_Reg64>; 1719 def : BitConvert <v4f32, v4i32, R600_Reg128>; 1720 def : BitConvert <v4i32, v4f32, R600_Reg128>; 1721 1722 // DWORDADDR pattern 1723 def : DwordAddrPat <i32, R600_Reg32>; 1724 1725 } // End isR600toCayman Predicate 1726 1727 def getLDSNoRetOp : InstrMapping { 1728 let FilterClass = "R600_LDS_1A1D"; 1729 let RowFields = ["BaseOp"]; 1730 let ColFields = ["DisableEncoding"]; 1731 let KeyCol = ["$dst"]; 1732 let ValueCols = [[""""]]; 1733 } 1734
