1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This is the top level entry point for the Mips target. 10 //===----------------------------------------------------------------------===// 11 12 //===----------------------------------------------------------------------===// 13 // Target-independent interfaces 14 //===----------------------------------------------------------------------===// 15 16 include "llvm/Target/Target.td" 17 18 // The overall idea of the PredicateControl class is to chop the Predicates list 19 // into subsets that are usually overridden independently. This allows 20 // subclasses to partially override the predicates of their superclasses without 21 // having to re-add all the existing predicates. 22 class PredicateControl { 23 // Predicates for the encoding scheme in use such as HasStdEnc 24 list<Predicate> EncodingPredicates = []; 25 // Predicates for the GPR size such as IsGP64bit 26 list<Predicate> GPRPredicates = []; 27 // Predicates for the PTR size such as IsPTR64bit 28 list<Predicate> PTRPredicates = []; 29 // Predicates for the FGR size and layout such as IsFP64bit 30 list<Predicate> FGRPredicates = []; 31 // Predicates for the instruction group membership such as ISA's and ASE's 32 list<Predicate> InsnPredicates = []; 33 // Predicate for marking the instruction as usable in hard-float mode only. 34 list<Predicate> HardFloatPredicate = []; 35 // Predicates for anything else 36 list<Predicate> AdditionalPredicates = []; 37 list<Predicate> Predicates = !listconcat(EncodingPredicates, 38 GPRPredicates, 39 PTRPredicates, 40 FGRPredicates, 41 InsnPredicates, 42 HardFloatPredicate, 43 AdditionalPredicates); 44 } 45 46 // Like Requires<> but for the AdditionalPredicates list 47 class AdditionalRequires<list<Predicate> preds> { 48 list<Predicate> AdditionalPredicates = preds; 49 } 50 51 //===----------------------------------------------------------------------===// 52 // Register File, Calling Conv, Instruction Descriptions 53 //===----------------------------------------------------------------------===// 54 55 include "MipsRegisterInfo.td" 56 include "MipsSchedule.td" 57 include "MipsInstrInfo.td" 58 include "MipsCallingConv.td" 59 60 def MipsInstrInfo : InstrInfo; 61 62 //===----------------------------------------------------------------------===// 63 // Mips Subtarget features // 64 //===----------------------------------------------------------------------===// 65 66 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true", 67 "Disable SVR4-style position-independent code">; 68 def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true", 69 "Pointers are 64-bit wide">; 70 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 71 "General Purpose Registers are 64-bit wide">; 72 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 73 "Support 64-bit FP registers">; 74 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true", 75 "Support for FPXX">; 76 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true", 77 "IEEE 754-2008 NaN encoding">; 78 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 79 "true", "Only supports single precision float">; 80 def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true", 81 "Does not support floating point instructions">; 82 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false", 83 "Disable odd numbered single-precision " 84 "registers">; 85 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 86 "true", "Enable vector FPU instructions">; 87 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", 88 "Mips I ISA Support [highly experimental]">; 89 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", 90 "Mips II ISA Support [highly experimental]", 91 [FeatureMips1]>; 92 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true", 93 "Subset of MIPS-III that is also in MIPS32 " 94 "[highly experimental]">; 95 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true", 96 "Subset of MIPS-III that is also in MIPS32r2 " 97 "[highly experimental]">; 98 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3", 99 "MIPS III ISA Support [highly experimental]", 100 [FeatureMips2, FeatureMips3_32, 101 FeatureMips3_32r2, FeatureGP64Bit, 102 FeatureFP64Bit]>; 103 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true", 104 "Subset of MIPS-IV that is also in MIPS32 " 105 "[highly experimental]">; 106 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true", 107 "Subset of MIPS-IV that is also in MIPS32r2 " 108 "[highly experimental]">; 109 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion", 110 "Mips4", "MIPS IV ISA Support", 111 [FeatureMips3, FeatureMips4_32, 112 FeatureMips4_32r2]>; 113 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true", 114 "Subset of MIPS-V that is also in MIPS32r2 " 115 "[highly experimental]">; 116 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5", 117 "MIPS V ISA Support [highly experimental]", 118 [FeatureMips4, FeatureMips5_32r2]>; 119 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 120 "Mips32 ISA Support", 121 [FeatureMips2, FeatureMips3_32, 122 FeatureMips4_32]>; 123 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 124 "Mips32r2", "Mips32r2 ISA Support", 125 [FeatureMips3_32r2, FeatureMips4_32r2, 126 FeatureMips5_32r2, FeatureMips32]>; 127 def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion", 128 "Mips32r3", "Mips32r3 ISA Support", 129 [FeatureMips32r2]>; 130 def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion", 131 "Mips32r5", "Mips32r5 ISA Support", 132 [FeatureMips32r3]>; 133 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion", 134 "Mips32r6", 135 "Mips32r6 ISA Support [experimental]", 136 [FeatureMips32r5, FeatureFP64Bit, 137 FeatureNaN2008]>; 138 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 139 "Mips64", "Mips64 ISA Support", 140 [FeatureMips5, FeatureMips32]>; 141 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 142 "Mips64r2", "Mips64r2 ISA Support", 143 [FeatureMips64, FeatureMips32r2]>; 144 def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion", 145 "Mips64r3", "Mips64r3 ISA Support", 146 [FeatureMips64r2, FeatureMips32r3]>; 147 def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion", 148 "Mips64r5", "Mips64r5 ISA Support", 149 [FeatureMips64r3, FeatureMips32r5]>; 150 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion", 151 "Mips64r6", 152 "Mips64r6 ISA Support [experimental]", 153 [FeatureMips32r6, FeatureMips64r5, 154 FeatureNaN2008]>; 155 156 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 157 "Mips16 mode">; 158 159 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 160 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 161 "Mips DSP-R2 ASE", [FeatureDSP]>; 162 def FeatureDSPR3 163 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE", 164 [ FeatureDSP, FeatureDSPR2 ]>; 165 166 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; 167 168 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">; 169 170 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", 171 "microMips mode">; 172 173 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips", 174 "true", "Octeon cnMIPS Support", 175 [FeatureMips64r2]>; 176 177 def FeatureUseTCCInDIV : SubtargetFeature< 178 "use-tcc-in-div", 179 "UseTCCInDIV", "false", 180 "Force the assembler to use trapping">; 181 182 //===----------------------------------------------------------------------===// 183 // Mips processors supported. 184 //===----------------------------------------------------------------------===// 185 186 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", 187 "MipsSubtarget::CPU::P5600", 188 "The P5600 Processor", [FeatureMips32r5]>; 189 190 class Proc<string Name, list<SubtargetFeature> Features> 191 : Processor<Name, MipsGenericItineraries, Features>; 192 193 def : Proc<"mips1", [FeatureMips1]>; 194 def : Proc<"mips2", [FeatureMips2]>; 195 def : Proc<"mips32", [FeatureMips32]>; 196 def : Proc<"mips32r2", [FeatureMips32r2]>; 197 def : Proc<"mips32r3", [FeatureMips32r3]>; 198 def : Proc<"mips32r5", [FeatureMips32r5]>; 199 def : Proc<"mips32r6", [FeatureMips32r6]>; 200 201 def : Proc<"mips3", [FeatureMips3]>; 202 def : Proc<"mips4", [FeatureMips4]>; 203 def : Proc<"mips5", [FeatureMips5]>; 204 def : Proc<"mips64", [FeatureMips64]>; 205 def : Proc<"mips64r2", [FeatureMips64r2]>; 206 def : Proc<"mips64r3", [FeatureMips64r3]>; 207 def : Proc<"mips64r5", [FeatureMips64r5]>; 208 def : Proc<"mips64r6", [FeatureMips64r6]>; 209 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>; 210 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>; 211 212 def MipsAsmParser : AsmParser { 213 let ShouldEmitMatchRegisterName = 0; 214 } 215 216 def MipsAsmParserVariant : AsmParserVariant { 217 int Variant = 0; 218 219 // Recognize hard coded registers. 220 string RegisterPrefix = "$"; 221 } 222 223 def Mips : Target { 224 let InstructionSet = MipsInstrInfo; 225 let AssemblyParsers = [MipsAsmParser]; 226 let AssemblyParserVariants = [MipsAsmParserVariant]; 227 } 228
