1 To-do 2 ----- 3 4 * Keep the address of the constant pool in a register instead of forming its 5 address all of the time. 6 * We can fold small constant offsets into the %hi/%lo references to constant 7 pool addresses as well. 8 * When in V9 mode, register allocate %icc[0-3]. 9 * Add support for isel'ing UMUL_LOHI instead of marking it as Expand. 10 * Emit the 'Branch on Integer Register with Prediction' instructions. It's 11 not clear how to write a pattern for this though: 12 13 float %t1(int %a, int* %p) { 14 %C = seteq int %a, 0 15 br bool %C, label %T, label %F 16 T: 17 store int 123, int* %p 18 br label %F 19 F: 20 ret float undef 21 } 22 23 codegens to this: 24 25 t1: 26 save -96, %o6, %o6 27 1) subcc %i0, 0, %l0 28 1) bne .LBBt1_2 ! F 29 nop 30 .LBBt1_1: ! T 31 or %g0, 123, %l0 32 st %l0, [%i1] 33 .LBBt1_2: ! F 34 restore %g0, %g0, %g0 35 retl 36 nop 37 38 1) should be replaced with a brz in V9 mode. 39 40 * Same as above, but emit conditional move on register zero (p192) in V9 41 mode. Testcase: 42 43 int %t1(int %a, int %b) { 44 %C = seteq int %a, 0 45 %D = select bool %C, int %a, int %b 46 ret int %D 47 } 48 49 * Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 50 with the Y register, if they are faster. 51 52 * Codegen bswap(load)/store(bswap) -> load/store ASI 53 54 * Implement frame pointer elimination, e.g. eliminate save/restore for 55 leaf fns. 56 * Fill delay slots 57 58 * Use %g0 directly to materialize 0. No instruction is required. 59
