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      1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 //===----------------------------------------------------------------------===//
     11 // Select instructions
     12 //===----------------------------------------------------------------------===//
     13 
     14 // C's ?: operator for floating-point operands.
     15 def SelectF32  : SelectWrapper<FP32>;
     16 def SelectF64  : SelectWrapper<FP64>;
     17 def SelectF128 : SelectWrapper<FP128>;
     18 
     19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
     20                                nonvolatile_load, bdxaddr20only>;
     21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
     22                                nonvolatile_load, bdxaddr20only>;
     23 
     24 //===----------------------------------------------------------------------===//
     25 // Move instructions
     26 //===----------------------------------------------------------------------===//
     27 
     28 // Load zero.
     29 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in {
     30   def LZER : InherentRRE<"lzer", 0xB374, FP32,  (fpimm0)>;
     31   def LZDR : InherentRRE<"lzdr", 0xB375, FP64,  (fpimm0)>;
     32   def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
     33 }
     34 
     35 // Moves between two floating-point registers.
     36 let hasSideEffects = 0 in {
     37   def LER : UnaryRR <"le", 0x38,   null_frag, FP32,  FP32>;
     38   def LDR : UnaryRR <"ld", 0x28,   null_frag, FP64,  FP64>;
     39   def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
     40 
     41   // For z13 we prefer LDR over LER to avoid partial register dependencies.
     42   let isCodeGenOnly = 1 in
     43     def LDR32 : UnaryRR<"ld", 0x28, null_frag, FP32, FP32>;
     44 }
     45 
     46 // Moves between two floating-point registers that also set the condition
     47 // codes.
     48 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
     49   defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
     50   defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
     51   defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
     52 }
     53 // Note that LTxBRCompare is not available if we have vector support,
     54 // since load-and-test instructions will partially clobber the target
     55 // (vector) register.
     56 let Predicates = [FeatureNoVector] in {
     57   defm : CompareZeroFP<LTEBRCompare, FP32>;
     58   defm : CompareZeroFP<LTDBRCompare, FP64>;
     59   defm : CompareZeroFP<LTXBRCompare, FP128>;
     60 }
     61 
     62 // Use a normal load-and-test for compare against zero in case of
     63 // vector support (via a pseudo to simplify instruction selection).
     64 let Defs = [CC], usesCustomInserter = 1 in {
     65   def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>;
     66   def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
     67   def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>;
     68 }
     69 let Predicates = [FeatureVector] in {
     70   defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>;
     71   defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
     72   defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>;
     73 }
     74 
     75 // Moves between 64-bit integer and floating-point registers.
     76 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
     77 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
     78 
     79 // fcopysign with an FP32 result.
     80 let isCodeGenOnly = 1 in {
     81   def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
     82   def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
     83 }
     84 
     85 // The sign of an FP128 is in the high register.
     86 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
     87           (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
     88 
     89 // fcopysign with an FP64 result.
     90 let isCodeGenOnly = 1 in
     91   def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
     92 def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
     93 
     94 // The sign of an FP128 is in the high register.
     95 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
     96           (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
     97 
     98 // fcopysign with an FP128 result.  Use "upper" as the high half and leave
     99 // the low half as-is.
    100 class CopySign128<RegisterOperand cls, dag upper>
    101   : Pat<(fcopysign FP128:$src1, cls:$src2),
    102         (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
    103 
    104 def : CopySign128<FP32,  (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
    105                                   FP32:$src2)>;
    106 def : CopySign128<FP64,  (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
    107                                   FP64:$src2)>;
    108 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
    109                                   (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
    110 
    111 defm LoadStoreF32  : MVCLoadStore<load, f32,  MVCSequence, 4>;
    112 defm LoadStoreF64  : MVCLoadStore<load, f64,  MVCSequence, 8>;
    113 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
    114 
    115 //===----------------------------------------------------------------------===//
    116 // Load instructions
    117 //===----------------------------------------------------------------------===//
    118 
    119 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
    120   defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
    121   defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
    122 
    123   // For z13 we prefer LDE over LE to avoid partial register dependencies.
    124   def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;
    125 
    126   // These instructions are split after register allocation, so we don't
    127   // want a custom inserter.
    128   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
    129     def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
    130                      [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
    131   }
    132 }
    133 
    134 //===----------------------------------------------------------------------===//
    135 // Store instructions
    136 //===----------------------------------------------------------------------===//
    137 
    138 let SimpleBDXStore = 1 in {
    139   defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
    140   defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
    141 
    142   // These instructions are split after register allocation, so we don't
    143   // want a custom inserter.
    144   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
    145     def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
    146                      [(store FP128:$src, bdxaddr20only128:$dst)]>;
    147   }
    148 }
    149 
    150 //===----------------------------------------------------------------------===//
    151 // Conversion instructions
    152 //===----------------------------------------------------------------------===//
    153 
    154 // Convert floating-point values to narrower representations, rounding
    155 // according to the current mode.  The destination of LEXBR and LDXBR
    156 // is a 128-bit value, but only the first register of the pair is used.
    157 def LEDBR : UnaryRRE<"ledb", 0xB344, fround,    FP32,  FP64>;
    158 def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
    159 def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
    160 
    161 def LEDBRA : UnaryRRF4<"ledbra", 0xB344, FP32,  FP64>,
    162              Requires<[FeatureFPExtension]>;
    163 def LEXBRA : UnaryRRF4<"lexbra", 0xB346, FP128, FP128>,
    164              Requires<[FeatureFPExtension]>;
    165 def LDXBRA : UnaryRRF4<"ldxbra", 0xB345, FP128, FP128>,
    166              Requires<[FeatureFPExtension]>;
    167 
    168 def : Pat<(f32 (fround FP128:$src)),
    169           (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>;
    170 def : Pat<(f64 (fround FP128:$src)),
    171           (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
    172 
    173 // Extend register floating-point values to wider representations.
    174 def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64,  FP32>;
    175 def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
    176 def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
    177 
    178 // Extend memory floating-point values to wider representations.
    179 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64,  4>;
    180 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
    181 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
    182 
    183 // Convert a signed integer register value to a floating-point one.
    184 def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32,  GR32>;
    185 def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64,  GR32>;
    186 def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
    187 
    188 def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32,  GR64>;
    189 def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64,  GR64>;
    190 def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
    191 
    192 // Convert am unsigned integer register value to a floating-point one.
    193 let Predicates = [FeatureFPExtension] in {
    194   def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32,  GR32>;
    195   def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64,  GR32>;
    196   def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>;
    197 
    198   def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32,  GR64>;
    199   def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64,  GR64>;
    200   def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>;
    201 
    202   def : Pat<(f32  (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
    203   def : Pat<(f64  (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
    204   def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
    205 
    206   def : Pat<(f32  (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
    207   def : Pat<(f64  (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
    208   def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
    209 }
    210 
    211 // Convert a floating-point register value to a signed integer value,
    212 // with the second operand (modifier M3) specifying the rounding mode.
    213 let Defs = [CC] in {
    214   def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
    215   def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
    216   def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
    217 
    218   def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
    219   def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
    220   def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
    221 }
    222 
    223 // fp_to_sint always rounds towards zero, which is modifier value 5.
    224 def : Pat<(i32 (fp_to_sint FP32:$src)),  (CFEBR 5, FP32:$src)>;
    225 def : Pat<(i32 (fp_to_sint FP64:$src)),  (CFDBR 5, FP64:$src)>;
    226 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
    227 
    228 def : Pat<(i64 (fp_to_sint FP32:$src)),  (CGEBR 5, FP32:$src)>;
    229 def : Pat<(i64 (fp_to_sint FP64:$src)),  (CGDBR 5, FP64:$src)>;
    230 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
    231 
    232 // Convert a floating-point register value to an unsigned integer value.
    233 let Predicates = [FeatureFPExtension] in {
    234   let Defs = [CC] in {
    235     def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>;
    236     def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>;
    237     def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>;
    238 
    239     def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>;
    240     def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>;
    241     def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>;
    242   }
    243 
    244   def : Pat<(i32 (fp_to_uint FP32:$src)),  (CLFEBR 5, FP32:$src,  0)>;
    245   def : Pat<(i32 (fp_to_uint FP64:$src)),  (CLFDBR 5, FP64:$src,  0)>;
    246   def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;
    247 
    248   def : Pat<(i64 (fp_to_uint FP32:$src)),  (CLGEBR 5, FP32:$src,  0)>;
    249   def : Pat<(i64 (fp_to_uint FP64:$src)),  (CLGDBR 5, FP64:$src,  0)>;
    250   def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;
    251 }
    252 
    253 
    254 //===----------------------------------------------------------------------===//
    255 // Unary arithmetic
    256 //===----------------------------------------------------------------------===//
    257 
    258 // We prefer generic instructions during isel, because they do not
    259 // clobber CC and therefore give the scheduler more freedom. In cases
    260 // the CC is actually useful, the SystemZElimCompare pass will try to
    261 // convert generic instructions into opcodes that also set CC. Note
    262 // that lcdf / lpdf / lndf only affect the sign bit, and can therefore
    263 // be used with fp32 as well. This could be done for fp128, in which
    264 // case the operands would have to be tied.
    265 
    266 // Negation (Load Complement).
    267 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    268   def LCEBR : UnaryRRE<"lceb", 0xB303, null_frag, FP32,  FP32>;
    269   def LCDBR : UnaryRRE<"lcdb", 0xB313, null_frag, FP64,  FP64>;
    270   def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
    271 }
    272 // Generic form, which does not set CC.
    273 def LCDFR : UnaryRRE<"lcdf", 0xB373, fneg, FP64,  FP64>;
    274 let isCodeGenOnly = 1 in
    275   def LCDFR_32 : UnaryRRE<"lcdf", 0xB373, fneg, FP32,  FP32>;
    276 
    277 // Absolute value (Load Positive).
    278 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    279   def LPEBR : UnaryRRE<"lpeb", 0xB300, null_frag, FP32,  FP32>;
    280   def LPDBR : UnaryRRE<"lpdb", 0xB310, null_frag, FP64,  FP64>;
    281   def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
    282 }
    283 // Generic form, which does not set CC.
    284 def LPDFR : UnaryRRE<"lpdf", 0xB370, fabs, FP64,  FP64>;
    285 let isCodeGenOnly = 1 in
    286   def LPDFR_32 : UnaryRRE<"lpdf", 0xB370, fabs, FP32,  FP32>;
    287 
    288 // Negative absolute value (Load Negative).
    289 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    290   def LNEBR : UnaryRRE<"lneb", 0xB301, null_frag, FP32,  FP32>;
    291   def LNDBR : UnaryRRE<"lndb", 0xB311, null_frag, FP64,  FP64>;
    292   def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
    293 }
    294 // Generic form, which does not set CC.
    295 def LNDFR : UnaryRRE<"lndf", 0xB371, fnabs, FP64,  FP64>;
    296 let isCodeGenOnly = 1 in
    297   def LNDFR_32 : UnaryRRE<"lndf", 0xB371, fnabs, FP32,  FP32>;
    298 
    299 // Square root.
    300 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32,  FP32>;
    301 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64,  FP64>;
    302 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
    303 
    304 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
    305 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
    306 
    307 // Round to an integer, with the second operand (modifier M3) specifying
    308 // the rounding mode.  These forms always check for inexact conditions.
    309 def FIEBR : UnaryRRF<"fieb", 0xB357, FP32,  FP32>;
    310 def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64,  FP64>;
    311 def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
    312 
    313 // frint rounds according to the current mode (modifier 0) and detects
    314 // inexact conditions.
    315 def : Pat<(frint FP32:$src),  (FIEBR 0, FP32:$src)>;
    316 def : Pat<(frint FP64:$src),  (FIDBR 0, FP64:$src)>;
    317 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
    318 
    319 let Predicates = [FeatureFPExtension] in {
    320   // Extended forms of the FIxBR instructions.  M4 can be set to 4
    321   // to suppress detection of inexact conditions.
    322   def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32,  FP32>;
    323   def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64,  FP64>;
    324   def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
    325 
    326   // fnearbyint is like frint but does not detect inexact conditions.
    327   def : Pat<(fnearbyint FP32:$src),  (FIEBRA 0, FP32:$src,  4)>;
    328   def : Pat<(fnearbyint FP64:$src),  (FIDBRA 0, FP64:$src,  4)>;
    329   def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
    330 
    331   // floor is no longer allowed to raise an inexact condition,
    332   // so restrict it to the cases where the condition can be suppressed.
    333   // Mode 7 is round towards -inf.
    334   def : Pat<(ffloor FP32:$src),  (FIEBRA 7, FP32:$src,  4)>;
    335   def : Pat<(ffloor FP64:$src),  (FIDBRA 7, FP64:$src,  4)>;
    336   def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
    337 
    338   // Same idea for ceil, where mode 6 is round towards +inf.
    339   def : Pat<(fceil FP32:$src),  (FIEBRA 6, FP32:$src,  4)>;
    340   def : Pat<(fceil FP64:$src),  (FIDBRA 6, FP64:$src,  4)>;
    341   def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
    342 
    343   // Same idea for trunc, where mode 5 is round towards zero.
    344   def : Pat<(ftrunc FP32:$src),  (FIEBRA 5, FP32:$src,  4)>;
    345   def : Pat<(ftrunc FP64:$src),  (FIDBRA 5, FP64:$src,  4)>;
    346   def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
    347 
    348   // Same idea for round, where mode 1 is round towards nearest with
    349   // ties away from zero.
    350   def : Pat<(frnd FP32:$src),  (FIEBRA 1, FP32:$src,  4)>;
    351   def : Pat<(frnd FP64:$src),  (FIDBRA 1, FP64:$src,  4)>;
    352   def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
    353 }
    354 
    355 //===----------------------------------------------------------------------===//
    356 // Binary arithmetic
    357 //===----------------------------------------------------------------------===//
    358 
    359 // Addition.
    360 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    361   let isCommutable = 1 in {
    362     def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32,  FP32>;
    363     def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64,  FP64>;
    364     def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
    365   }
    366   def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
    367   def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
    368 }
    369 
    370 // Subtraction.
    371 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    372   def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32,  FP32>;
    373   def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64,  FP64>;
    374   def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
    375 
    376   def SEB : BinaryRXE<"seb",  0xED0B, fsub, FP32, load, 4>;
    377   def SDB : BinaryRXE<"sdb",  0xED1B, fsub, FP64, load, 8>;
    378 }
    379 
    380 // Multiplication.
    381 let isCommutable = 1 in {
    382   def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32,  FP32>;
    383   def MDBR  : BinaryRRE<"mdb",  0xB31C, fmul, FP64,  FP64>;
    384   def MXBR  : BinaryRRE<"mxb",  0xB34C, fmul, FP128, FP128>;
    385 }
    386 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
    387 def MDB  : BinaryRXE<"mdb",  0xED1C, fmul, FP64, load, 8>;
    388 
    389 // f64 multiplication of two FP32 registers.
    390 def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
    391 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
    392           (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
    393                                 FP32:$src1, subreg_r32), FP32:$src2)>;
    394 
    395 // f64 multiplication of an FP32 register and an f32 memory.
    396 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
    397 def : Pat<(fmul (f64 (fextend FP32:$src1)),
    398                 (f64 (extloadf32 bdxaddr12only:$addr))),
    399           (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32),
    400                 bdxaddr12only:$addr)>;
    401 
    402 // f128 multiplication of two FP64 registers.
    403 def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
    404 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
    405           (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
    406                                 FP64:$src1, subreg_h64), FP64:$src2)>;
    407 
    408 // f128 multiplication of an FP64 register and an f64 memory.
    409 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
    410 def : Pat<(fmul (f128 (fextend FP64:$src1)),
    411                 (f128 (extloadf64 bdxaddr12only:$addr))),
    412           (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
    413                 bdxaddr12only:$addr)>;
    414 
    415 // Fused multiply-add.
    416 def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
    417 def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
    418 
    419 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
    420 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
    421 
    422 // Fused multiply-subtract.
    423 def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
    424 def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
    425 
    426 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
    427 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
    428 
    429 // Division.
    430 def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32,  FP32>;
    431 def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64,  FP64>;
    432 def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
    433 
    434 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
    435 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
    436 
    437 //===----------------------------------------------------------------------===//
    438 // Comparisons
    439 //===----------------------------------------------------------------------===//
    440 
    441 let Defs = [CC], CCValues = 0xF in {
    442   def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32,  FP32>;
    443   def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64,  FP64>;
    444   def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
    445 
    446   def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
    447   def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
    448 }
    449 
    450 // Test Data Class.
    451 let Defs = [CC], CCValues = 0xC in {
    452   def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>;
    453   def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>;
    454   def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>;
    455 }
    456 
    457 //===----------------------------------------------------------------------===//
    458 // Peepholes
    459 //===----------------------------------------------------------------------===//
    460 
    461 def : Pat<(f32  fpimmneg0), (LCDFR_32 (LZER))>;
    462 def : Pat<(f64  fpimmneg0), (LCDFR (LZDR))>;
    463 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
    464