1 //===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // Record that INSN performs a 64-bit version of unary operator OPERATOR 11 // in which the operand is sign-extended from 32 to 64 bits. 12 multiclass SXU<SDPatternOperator operator, Instruction insn> { 13 def : Pat<(operator (sext (i32 GR32:$src))), 14 (insn GR32:$src)>; 15 def : Pat<(operator (sext_inreg GR64:$src, i32)), 16 (insn (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 17 } 18 19 // Record that INSN performs a 64-bit version of binary operator OPERATOR 20 // in which the first operand has class CLS and which the second operand 21 // is sign-extended from a 32-bit register. 22 multiclass SXB<SDPatternOperator operator, RegisterOperand cls, 23 Instruction insn> { 24 def : Pat<(operator cls:$src1, (sext GR32:$src2)), 25 (insn cls:$src1, GR32:$src2)>; 26 def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)), 27 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>; 28 } 29 30 // Like SXB, but for zero extension. 31 multiclass ZXB<SDPatternOperator operator, RegisterOperand cls, 32 Instruction insn> { 33 def : Pat<(operator cls:$src1, (zext GR32:$src2)), 34 (insn cls:$src1, GR32:$src2)>; 35 def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)), 36 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>; 37 } 38 39 // Record that INSN performs a binary read-modify-write operation, 40 // with LOAD, OPERATOR and STORE being the read, modify and write 41 // respectively. MODE is the addressing mode and IMM is the type 42 // of the second operand. 43 class RMWI<SDPatternOperator load, SDPatternOperator operator, 44 SDPatternOperator store, AddressingMode mode, 45 PatFrag imm, Instruction insn> 46 : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr), 47 (insn mode:$addr, (UIMM8 imm:$src))>; 48 49 // Record that INSN performs binary operation OPERATION on a byte 50 // memory location. IMM is the type of the second operand. 51 multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode, 52 Instruction insn> { 53 def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>; 54 def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>; 55 } 56 57 // Record that INSN performs insertion TYPE into a register of class CLS. 58 // The inserted operand is loaded using LOAD from an address of mode MODE. 59 multiclass InsertMem<string type, Instruction insn, RegisterOperand cls, 60 SDPatternOperator load, AddressingMode mode> { 61 def : Pat<(!cast<SDPatternOperator>("or_as_"##type) 62 cls:$src1, (load mode:$src2)), 63 (insn cls:$src1, mode:$src2)>; 64 def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type) 65 (load mode:$src2), cls:$src1), 66 (insn cls:$src1, mode:$src2)>; 67 } 68 69 // INSN stores the low 32 bits of a GPR to a memory with addressing mode MODE. 70 // Record that it is equivalent to using OPERATOR to store a GR64. 71 class StoreGR64<Instruction insn, SDPatternOperator operator, 72 AddressingMode mode> 73 : Pat<(operator GR64:$R1, mode:$XBD2), 74 (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), mode:$XBD2)>; 75 76 // INSN and INSNY are an RX/RXY pair of instructions that store the low 77 // 32 bits of a GPR to memory. Record that they are equivalent to using 78 // OPERATOR to store a GR64. 79 multiclass StoreGR64Pair<Instruction insn, Instruction insny, 80 SDPatternOperator operator> { 81 def : StoreGR64<insn, operator, bdxaddr12pair>; 82 def : StoreGR64<insny, operator, bdxaddr20pair>; 83 } 84 85 // INSN stores the low 32 bits of a GPR using PC-relative addressing. 86 // Record that it is equivalent to using OPERATOR to store a GR64. 87 class StoreGR64PC<Instruction insn, SDPatternOperator operator> 88 : Pat<(operator GR64:$R1, pcrel32:$XBD2), 89 (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), pcrel32:$XBD2)> { 90 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 91 // However, BDXs have two extra operands and are therefore 6 units more 92 // complex. 93 let AddedComplexity = 7; 94 } 95 96 // INSN and INSNINV conditionally store the low 32 bits of a GPR to memory, 97 // with INSN storing when the condition is true and INSNINV storing when the 98 // condition is false. Record that they are equivalent to a LOAD/select/STORE 99 // sequence for GR64s. 100 multiclass CondStores64<Instruction insn, Instruction insninv, 101 SDPatternOperator store, SDPatternOperator load, 102 AddressingMode mode> { 103 def : Pat<(store (z_select_ccmask GR64:$new, (load mode:$addr), 104 imm32zx4:$valid, imm32zx4:$cc), 105 mode:$addr), 106 (insn (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr, 107 imm32zx4:$valid, imm32zx4:$cc)>; 108 def : Pat<(store (z_select_ccmask (load mode:$addr), GR64:$new, 109 imm32zx4:$valid, imm32zx4:$cc), 110 mode:$addr), 111 (insninv (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr, 112 imm32zx4:$valid, imm32zx4:$cc)>; 113 } 114 115 // Try to use MVC instruction INSN for a load of type LOAD followed by a store 116 // of the same size. VT is the type of the intermediate (legalized) value and 117 // LENGTH is the number of bytes loaded by LOAD. 118 multiclass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn, 119 bits<5> length> { 120 def : Pat<(mvc_store (vt (load bdaddr12only:$src)), bdaddr12only:$dest), 121 (insn bdaddr12only:$dest, bdaddr12only:$src, length)>; 122 } 123 124 // Use NC-like instruction INSN for block_op operation OPERATOR. 125 // The other operand is a load of type LOAD, which accesses LENGTH bytes. 126 // VT is the intermediate legalized type in which the binary operation 127 // is actually done. 128 multiclass BinaryLoadStore<SDPatternOperator operator, SDPatternOperator load, 129 ValueType vt, Instruction insn, bits<5> length> { 130 def : Pat<(operator (vt (load bdaddr12only:$src)), bdaddr12only:$dest), 131 (insn bdaddr12only:$dest, bdaddr12only:$src, length)>; 132 } 133 134 // A convenient way of generating all block peepholes for a particular 135 // LOAD/VT/LENGTH combination. 136 multiclass BlockLoadStore<SDPatternOperator load, ValueType vt, 137 Instruction mvc, Instruction nc, Instruction oc, 138 Instruction xc, bits<5> length> { 139 defm : MVCLoadStore<load, vt, mvc, length>; 140 defm : BinaryLoadStore<block_and1, load, vt, nc, length>; 141 defm : BinaryLoadStore<block_and2, load, vt, nc, length>; 142 defm : BinaryLoadStore<block_or1, load, vt, oc, length>; 143 defm : BinaryLoadStore<block_or2, load, vt, oc, length>; 144 defm : BinaryLoadStore<block_xor1, load, vt, xc, length>; 145 defm : BinaryLoadStore<block_xor2, load, vt, xc, length>; 146 } 147 148 // Record that INSN is a LOAD AND TEST that can be used to compare 149 // registers in CLS against zero. The instruction has separate R1 and R2 150 // operands, but they must be the same when the instruction is used like this. 151 multiclass CompareZeroFP<Instruction insn, RegisterOperand cls> { 152 def : Pat<(z_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>; 153 // The sign of the zero makes no difference. 154 def : Pat<(z_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg, cls:$reg)>; 155 } 156 157 // Use INSN for performing binary operation OPERATION of type VT 158 // on registers of class CLS. 159 class BinaryRRWithType<Instruction insn, RegisterOperand cls, 160 SDPatternOperator operator, ValueType vt> 161 : Pat<(vt (operator cls:$x, cls:$y)), (insn cls:$x, cls:$y)>; 162 163 // Use INSN to perform conversion operation OPERATOR, with the input being 164 // TR2 and the output being TR1. SUPPRESS is 4 to suppress inexact conditions 165 // and 0 to allow them. MODE is the rounding mode to use. 166 class FPConversion<Instruction insn, SDPatternOperator operator, TypedReg tr1, 167 TypedReg tr2, bits<3> suppress, bits<4> mode> 168 : Pat<(tr1.vt (operator (tr2.vt tr2.op:$vec))), 169 (insn tr2.op:$vec, suppress, mode)>; 170
