1 //===-- XCoreRegisterInfo.td - XCore Register defs ---------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the XCore register file 12 //===----------------------------------------------------------------------===// 13 14 class XCoreReg<string n> : Register<n> { 15 field bits<4> Num; 16 let Namespace = "XCore"; 17 } 18 19 // Registers are identified with 4-bit ID numbers. 20 // Ri - 32-bit integer registers 21 class Ri<bits<4> num, string n> : XCoreReg<n> { 22 let Num = num; 23 } 24 25 // CPU registers 26 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; 27 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; 28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; 29 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; 30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>; 31 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>; 32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>; 33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>; 34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>; 35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>; 36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; 37 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>; 38 def CP : Ri<12, "cp">, DwarfRegNum<[12]>; 39 def DP : Ri<13, "dp">, DwarfRegNum<[13]>; 40 def SP : Ri<14, "sp">, DwarfRegNum<[14]>; 41 def LR : Ri<15, "lr">, DwarfRegNum<[15]>; 42 43 // Register classes. 44 // 45 def GRRegs : RegisterClass<"XCore", [i32], 32, 46 // Return values and arguments 47 (add R0, R1, R2, R3, 48 // Callee save 49 R4, R5, R6, R7, R8, R9, R10, 50 // Not preserved across procedure calls 51 R11)>; 52 53 // Reserved 54 def RRegs : RegisterClass<"XCore", [i32], 32, 55 (add R0, R1, R2, R3, 56 R4, R5, R6, R7, R8, R9, R10, 57 R11, CP, DP, SP, LR)> { 58 let isAllocatable = 0; 59 } 60
