1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4 ; GCN-LABEL: {{^}}main: 5 ; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} 6 ; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1 7 define amdgpu_ps void @main(float %arg0, float %arg1) #0 { 8 bb: 9 %tmp = fptosi float %arg0 to i32 10 %tmp1 = call <4 x float> @llvm.SI.image.load.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 11 %tmp2.f = extractelement <4 x float> %tmp1, i32 0 12 %tmp2 = bitcast float %tmp2.f to i32 13 %tmp3 = and i32 %tmp, 7 14 %tmp4 = shl i32 1, %tmp3 15 %tmp5 = and i32 %tmp2, %tmp4 16 %tmp6 = icmp eq i32 %tmp5, 0 17 %tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1 18 %tmp8 = call i32 @llvm.SI.packf16(float undef, float %tmp7) 19 %tmp9 = bitcast i32 %tmp8 to float 20 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %tmp9, float undef, float %tmp9) 21 ret void 22 } 23 24 declare <4 x float> @llvm.SI.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 25 declare i32 @llvm.SI.packf16(float, float) #1 26 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 27 28 attributes #0 = { nounwind } 29 attributes #1 = { nounwind readnone } 30
