1 ; RUN: llc -mtriple=thumbv7-apple-ios8.0 %s -o - | FileCheck %s 2 3 ; This checks that alignments greater than 4 are respected by APCS 4 ; targets. Mostly here to make sure *some* correct code is created after some 5 ; simplifying refactoring; at the time of writing there were no actual APCS 6 ; users of byval alignments > 4, so no real calls for ABI stability. 7 8 ; "byval align 16" can't fit in any regs with an i8* taking up r0. 9 define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) { 10 ; CHECK-LABEL: test_align16: 11 ; CHECK-NOT: sub sp 12 ; CHECK: push {r4, r7, lr} 13 ; CHECK: add r7, sp, #4 14 15 ; CHECK: ldr r0, [r7, #8] 16 17 call void @bar() 18 %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0 19 %val = load i32, i32* %valptr 20 ret i32 %val 21 } 22 23 ; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the 24 ; space taken up by arg regs). 25 define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) { 26 ; CHECK-LABEL: test_align8: 27 ; CHECK: sub sp, #8 28 ; CHECK: push {r4, r7, lr} 29 ; CHECK: add r7, sp, #4 30 31 ; CHECK: strd r2, r3, [r7, #8] 32 33 ; CHECK: ldr r0, [r7, #8] 34 35 call void @bar() 36 %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0 37 %val = load i32, i32* %valptr 38 ret i32 %val 39 } 40 41 ; "byval align 32" can't fit in regs no matter what: it would be misaligned 42 ; unless the incoming stack was deliberately misaligned. 43 define i32 @test_align32(i8*, [4 x i32]* byval align 32 %b) { 44 ; CHECK-LABEL: test_align32: 45 ; CHECK-NOT: sub sp 46 ; CHECK: push {r4, r7, lr} 47 ; CHECK: add r7, sp, #4 48 49 ; CHECK: ldr r0, [r7, #8] 50 51 call void @bar() 52 %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0 53 %val = load i32, i32* %valptr 54 ret i32 %val 55 } 56 57 ; When passing an object "byval align N", the stack must be at least N-aligned. 58 define void @test_call_align16() { 59 ; CHECK-LABEL: test_call_align16: 60 ; CHECK: push {r4, r7, lr} 61 ; CHECK: add r7, sp, #4 62 63 ; CHECK: mov [[TMP:r[0-9]+]], sp 64 ; CHECK: bfc [[TMP]], #0, #4 65 ; CHECK: mov sp, [[TMP]] 66 67 ; While we're here, make sure the caller also puts it at sp 68 ; CHECK: mov r[[BASE:[0-9]+]], sp 69 ; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]] 70 call i32 @test_align16(i8* null, [4 x i32]* byval align 16 @var) 71 ret void 72 } 73 74 @var = global [4 x i32] zeroinitializer 75 declare void @bar() 76
