1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ 2 ; RUN: | FileCheck %s -check-prefix=VFP2 3 4 ; RUN: llc -mtriple=arm-eabi -mattr=+neon,-neonfp %s -o - \ 5 ; RUN: | FileCheck %s -check-prefix=NFP0 6 7 ; RUN: llc -mtriple=arm-eabi -mattr=+neon,+neonfp %s -o - \ 8 ; RUN: | FileCheck %s -check-prefix=NFP1 9 10 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \ 11 ; RUN: | FileCheck %s -check-prefix=CORTEXA8 12 13 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \ 14 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U 15 16 ; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \ 17 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U 18 19 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \ 20 ; RUN: | FileCheck %s -check-prefix=CORTEXA9 21 22 define float @test1(float* %a) { 23 entry: 24 %0 = load float, float* %a, align 4 ; <float> [#uses=2] 25 %1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2] 26 %2 = fpext float %1 to double ; <double> [#uses=1] 27 %3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1] 28 %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1] 29 ret float %retval 30 } 31 ; VFP2-LABEL: test1: 32 ; VFP2: vneg.f32 s{{.*}}, s{{.*}} 33 34 ; NFP1-LABEL: test1: 35 ; NFP1: vneg.f32 d{{.*}}, d{{.*}} 36 37 ; NFP0-LABEL: test1: 38 ; NFP0: vneg.f32 s{{.*}}, s{{.*}} 39 40 ; CORTEXA8-LABEL: test1: 41 ; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}} 42 43 ; CORTEXA8U-LABEL: test1: 44 ; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}} 45 46 ; CORTEXA9-LABEL: test1: 47 ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} 48 49 define float @test2(float* %a) { 50 entry: 51 %0 = load float, float* %a, align 4 ; <float> [#uses=2] 52 %1 = fmul float -1.000000e+00, %0 ; <float> [#uses=2] 53 %2 = fpext float %1 to double ; <double> [#uses=1] 54 %3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1] 55 %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1] 56 ret float %retval 57 } 58 ; VFP2-LABEL: test2: 59 ; VFP2: vneg.f32 s{{.*}}, s{{.*}} 60 61 ; NFP1-LABEL: test2: 62 ; NFP1: vneg.f32 d{{.*}}, d{{.*}} 63 64 ; NFP0-LABEL: test2: 65 ; NFP0: vneg.f32 s{{.*}}, s{{.*}} 66 67 ; CORTEXA8-LABEL: test2: 68 ; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}} 69 70 ; CORTEXA8U-LABEL: test2: 71 ; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}} 72 73 ; CORTEXA9-LABEL: test2: 74 ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} 75 76 ; If we're bitcasting an integer to an FP vector, we should avoid the FP/vector unit entirely. 77 ; Make sure that we're flipping the sign bit and only the sign bit of each float (PR20354). 78 ; So instead of something like this: 79 ; vmov d16, r0, r1 80 ; vneg.f32 d16, d16 81 ; vmov r0, r1, d16 82 ; 83 ; We should generate: 84 ; eor r0, r0, #-214783648 85 ; eor r1, r1, #-214783648 86 87 define <2 x float> @fneg_bitcast(i64 %i) { 88 %bitcast = bitcast i64 %i to <2 x float> 89 %fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast 90 ret <2 x float> %fneg 91 } 92 ; VFP2-LABEL: fneg_bitcast: 93 ; VFP2-DAG: eor r0, r0, #-2147483648 94 ; VFP2-DAG: eor r1, r1, #-2147483648 95 ; VFP2-NOT: vneg.f32 96 97 ; NFP1-LABEL: fneg_bitcast: 98 ; NFP1-DAG: eor r0, r0, #-2147483648 99 ; NFP1-DAG: eor r1, r1, #-2147483648 100 ; NFP1-NOT: vneg.f32 101 102 ; NFP0-LABEL: fneg_bitcast: 103 ; NFP0-DAG: eor r0, r0, #-2147483648 104 ; NFP0-DAG: eor r1, r1, #-2147483648 105 ; NFP0-NOT: vneg.f32 106 107 ; CORTEXA8-LABEL: fneg_bitcast: 108 ; CORTEXA8-DAG: eor r0, r0, #-2147483648 109 ; CORTEXA8-DAG: eor r1, r1, #-2147483648 110 ; CORTEXA8-NOT: vneg.f32 111 112 ; CORTEXA8U-LABEL: fneg_bitcast: 113 ; CORTEXA8U-DAG: eor r0, r0, #-2147483648 114 ; CORTEXA8U-DAG: eor r1, r1, #-2147483648 115 ; CORTEXA8U-NOT: vneg.f32 116 117 ; CORTEXA9-LABEL: fneg_bitcast: 118 ; CORTEXA9-DAG: eor r0, r0, #-2147483648 119 ; CORTEXA9-DAG: eor r1, r1, #-2147483648 120 ; CORTEXA9-NOT: vneg.f32 121 122
