1 ; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s 2 ; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s 3 4 define void @coproc(i8* %i) nounwind { 5 entry: 6 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4 7 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind 8 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4 9 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind 10 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4 11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind 12 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4 13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind 14 ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1 15 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind 16 ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1 17 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind 18 ; CHECK: cdp p7, #3, c1, c1, c1, #5 19 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind 20 ; CHECK: cdp2 p7, #3, c1, c1, c1, #5 21 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind 22 ; CHECK: ldc p7, c3, [r{{[0-9]+}}] 23 tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind 24 ; CHECK: ldcl p7, c3, [r{{[0-9]+}}] 25 tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind 26 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}] 27 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind 28 ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}] 29 tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind 30 ; CHECK: stc p7, c3, [r{{[0-9]+}}] 31 tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind 32 ; CHECK: stcl p7, c3, [r{{[0-9]+}}] 33 tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind 34 ; CHECK: stc2 p7, c3, [r{{[0-9]+}}] 35 tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind 36 ; CHECK: stc2l p7, c3, [r{{[0-9]+}}] 37 tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind 38 ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 39 %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind 40 ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 41 %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind 42 ret void 43 } 44 45 declare void @llvm.arm.ldc(i32, i32, i8*) nounwind 46 47 declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind 48 49 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind 50 51 declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind 52 53 declare void @llvm.arm.stc(i32, i32, i8*) nounwind 54 55 declare void @llvm.arm.stcl(i32, i32, i8*) nounwind 56 57 declare void @llvm.arm.stc2(i32, i32, i8*) nounwind 58 59 declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind 60 61 declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind 62 63 declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind 64 65 declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind 66 67 declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind 68 69 declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind 70 71 declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind 72 73 declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind 74 75 declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind 76 77 declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind 78 79 declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind 80
