1 ; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE 2 ; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE 3 ; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE 4 5 ; ACORE: LLVM ERROR: Invalid register name "control". 6 ; M3CORE: LLVM ERROR: Invalid register name "xpsr_nzcvqg". 7 8 define i32 @read_mclass_registers() nounwind { 9 entry: 10 ; MCORE-LABEL: read_mclass_registers: 11 ; MCORE: mrs r0, apsr 12 ; MCORE: mrs r1, iapsr 13 ; MCORE: mrs r1, eapsr 14 ; MCORE: mrs r1, xpsr 15 ; MCORE: mrs r1, ipsr 16 ; MCORE: mrs r1, epsr 17 ; MCORE: mrs r1, iepsr 18 ; MCORE: mrs r1, msp 19 ; MCORE: mrs r1, psp 20 ; MCORE: mrs r1, primask 21 ; MCORE: mrs r1, basepri 22 ; MCORE: mrs r1, basepri_max 23 ; MCORE: mrs r1, faultmask 24 ; MCORE: mrs r1, control 25 26 %0 = call i32 @llvm.read_register.i32(metadata !0) 27 %1 = call i32 @llvm.read_register.i32(metadata !4) 28 %add1 = add i32 %1, %0 29 %2 = call i32 @llvm.read_register.i32(metadata !8) 30 %add2 = add i32 %add1, %2 31 %3 = call i32 @llvm.read_register.i32(metadata !12) 32 %add3 = add i32 %add2, %3 33 %4 = call i32 @llvm.read_register.i32(metadata !16) 34 %add4 = add i32 %add3, %4 35 %5 = call i32 @llvm.read_register.i32(metadata !17) 36 %add5 = add i32 %add4, %5 37 %6 = call i32 @llvm.read_register.i32(metadata !18) 38 %add6 = add i32 %add5, %6 39 %7 = call i32 @llvm.read_register.i32(metadata !19) 40 %add7 = add i32 %add6, %7 41 %8 = call i32 @llvm.read_register.i32(metadata !20) 42 %add8 = add i32 %add7, %8 43 %9 = call i32 @llvm.read_register.i32(metadata !21) 44 %add9 = add i32 %add8, %9 45 %10 = call i32 @llvm.read_register.i32(metadata !22) 46 %add10 = add i32 %add9, %10 47 %11 = call i32 @llvm.read_register.i32(metadata !23) 48 %add11 = add i32 %add10, %11 49 %12 = call i32 @llvm.read_register.i32(metadata !24) 50 %add12 = add i32 %add11, %12 51 %13 = call i32 @llvm.read_register.i32(metadata !25) 52 %add13 = add i32 %add12, %13 53 ret i32 %add13 54 } 55 56 define void @write_mclass_registers(i32 %x) nounwind { 57 entry: 58 ; MCORE-LABEL: write_mclass_registers: 59 ; MCORE: msr apsr_nzcvqg, r0 60 ; MCORE: msr apsr_nzcvq, r0 61 ; MCORE: msr apsr_g, r0 62 ; MCORE: msr apsr_nzcvqg, r0 63 ; MCORE: msr iapsr_nzcvqg, r0 64 ; MCORE: msr iapsr_nzcvq, r0 65 ; MCORE: msr iapsr_g, r0 66 ; MCORE: msr iapsr_nzcvqg, r0 67 ; MCORE: msr eapsr_nzcvqg, r0 68 ; MCORE: msr eapsr_nzcvq, r0 69 ; MCORE: msr eapsr_g, r0 70 ; MCORE: msr eapsr_nzcvqg, r0 71 ; MCORE: msr xpsr_nzcvqg, r0 72 ; MCORE: msr xpsr_nzcvq, r0 73 ; MCORE: msr xpsr_g, r0 74 ; MCORE: msr xpsr_nzcvqg, r0 75 ; MCORE: msr ipsr, r0 76 ; MCORE: msr epsr, r0 77 ; MCORE: msr iepsr, r0 78 ; MCORE: msr msp, r0 79 ; MCORE: msr psp, r0 80 ; MCORE: msr primask, r0 81 ; MCORE: msr basepri, r0 82 ; MCORE: msr basepri_max, r0 83 ; MCORE: msr faultmask, r0 84 ; MCORE: msr control, r0 85 86 call void @llvm.write_register.i32(metadata !0, i32 %x) 87 call void @llvm.write_register.i32(metadata !1, i32 %x) 88 call void @llvm.write_register.i32(metadata !2, i32 %x) 89 call void @llvm.write_register.i32(metadata !3, i32 %x) 90 call void @llvm.write_register.i32(metadata !4, i32 %x) 91 call void @llvm.write_register.i32(metadata !5, i32 %x) 92 call void @llvm.write_register.i32(metadata !6, i32 %x) 93 call void @llvm.write_register.i32(metadata !7, i32 %x) 94 call void @llvm.write_register.i32(metadata !8, i32 %x) 95 call void @llvm.write_register.i32(metadata !9, i32 %x) 96 call void @llvm.write_register.i32(metadata !10, i32 %x) 97 call void @llvm.write_register.i32(metadata !11, i32 %x) 98 call void @llvm.write_register.i32(metadata !12, i32 %x) 99 call void @llvm.write_register.i32(metadata !13, i32 %x) 100 call void @llvm.write_register.i32(metadata !14, i32 %x) 101 call void @llvm.write_register.i32(metadata !15, i32 %x) 102 call void @llvm.write_register.i32(metadata !16, i32 %x) 103 call void @llvm.write_register.i32(metadata !17, i32 %x) 104 call void @llvm.write_register.i32(metadata !18, i32 %x) 105 call void @llvm.write_register.i32(metadata !19, i32 %x) 106 call void @llvm.write_register.i32(metadata !20, i32 %x) 107 call void @llvm.write_register.i32(metadata !21, i32 %x) 108 call void @llvm.write_register.i32(metadata !22, i32 %x) 109 call void @llvm.write_register.i32(metadata !23, i32 %x) 110 call void @llvm.write_register.i32(metadata !24, i32 %x) 111 call void @llvm.write_register.i32(metadata !25, i32 %x) 112 ret void 113 } 114 115 declare i32 @llvm.read_register.i32(metadata) nounwind 116 declare void @llvm.write_register.i32(metadata, i32) nounwind 117 118 !0 = !{!"apsr"} 119 !1 = !{!"apsr_nzcvq"} 120 !2 = !{!"apsr_g"} 121 !3 = !{!"apsr_nzcvqg"} 122 !4 = !{!"iapsr"} 123 !5 = !{!"iapsr_nzcvq"} 124 !6 = !{!"iapsr_g"} 125 !7 = !{!"iapsr_nzcvqg"} 126 !8 = !{!"eapsr"} 127 !9 = !{!"eapsr_nzcvq"} 128 !10 = !{!"eapsr_g"} 129 !11 = !{!"eapsr_nzcvqg"} 130 !12 = !{!"xpsr"} 131 !13 = !{!"xpsr_nzcvq"} 132 !14 = !{!"xpsr_g"} 133 !15 = !{!"xpsr_nzcvqg"} 134 !16 = !{!"ipsr"} 135 !17 = !{!"epsr"} 136 !18 = !{!"iepsr"} 137 !19 = !{!"msp"} 138 !20 = !{!"psp"} 139 !21 = !{!"primask"} 140 !22 = !{!"basepri"} 141 !23 = !{!"basepri_max"} 142 !24 = !{!"faultmask"} 143 !25 = !{!"control"} 144
