1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s 2 ; REQUIRES: asserts 3 4 ; Test that the accessSize is set on a post-increment store. If not, an assert 5 ; is triggered in getBaseAndOffset() 6 7 %struct.A = type { i8, i32, i32, i32, [10 x i32], [10 x i32], [80 x i32], [80 x i32], [8 x i32], i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 } 8 9 ; Function Attrs: nounwind 10 define fastcc void @Decoder_amr(i8 zeroext %mode) #0 { 11 entry: 12 br label %for.cond64.preheader.i 13 14 for.cond64.preheader.i: 15 %i.1984.i = phi i32 [ 0, %entry ], [ %inc166.i.1, %for.cond64.preheader.i ] 16 %inc166.i = add nsw i32 %i.1984.i, 1 17 %arrayidx71.i1422.1 = getelementptr inbounds %struct.A, %struct.A* undef, i32 0, i32 7, i32 %inc166.i 18 %storemerge800.i.1 = select i1 undef, i32 1310, i32 undef 19 %sub156.i.1 = sub nsw i32 0, %storemerge800.i.1 20 %sub156.storemerge800.i.1 = select i1 undef, i32 %storemerge800.i.1, i32 %sub156.i.1 21 store i32 %sub156.storemerge800.i.1, i32* %arrayidx71.i1422.1, align 4 22 store i32 0, i32* undef, align 4 23 %inc166.i.1 = add nsw i32 %i.1984.i, 2 24 br label %for.cond64.preheader.i 25 26 if.end: 27 ret void 28 } 29 30 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 31
