1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; CHECK: = vmem(r{{[0-9]+}}++#1) 3 4 target triple = "hexagon-unknown--elf" 5 6 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0 7 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #0 8 declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #0 9 declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0 10 declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0 11 declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0 12 declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0 13 14 define void @fred() #1 { 15 entry: 16 br i1 undef, label %b1, label %call_destructor.exit 17 18 b1: ; preds = %entry 19 br label %b2 20 21 b2: ; preds = %b1, %b2 22 %c2.host32.sroa.3.0 = phi <128 x i8> [ %5, %b2 ], [ undef, %b1 ] 23 %sobel_halide.s0.x.x = phi i32 [ %17, %b2 ], [ 0, %b1 ] 24 %0 = add nsw i32 %sobel_halide.s0.x.x, undef 25 %1 = shl i32 %0, 7 26 %2 = add nsw i32 %1, 128 27 %3 = getelementptr inbounds i8, i8* undef, i32 %2 28 %4 = bitcast i8* %3 to <128 x i8>* 29 %5 = load <128 x i8>, <128 x i8>* %4, align 128 30 %6 = bitcast <128 x i8> %c2.host32.sroa.3.0 to <32 x i32> 31 %7 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %6, i32 1) 32 %8 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %7) #1 33 %9 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %8) #1 34 %10 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %9, <64 x i32> undef) #1 35 %11 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %10) 36 %12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %11) #1 37 %13 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %12, <32 x i32> undef) 38 %14 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %13) #1 39 %15 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %14) #1 40 %16 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %15, <32 x i32> undef) #1 41 store <32 x i32> %16, <32 x i32>* undef, align 128 42 %17 = add nuw nsw i32 %sobel_halide.s0.x.x, 1 43 br label %b2 44 45 call_destructor.exit: ; preds = %entry 46 ret void 47 } 48 49 declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 50 51 attributes #0 = { nounwind readnone } 52 attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } 53
