1 # RUN: llc -mtriple thumbv7 -verify-machineinstrs -start-after if-converter -print-before post-RA-sched -print-after post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s 2 --- | 3 ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' 4 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5 target triple = "thumbv7" 6 7 %struct.s = type opaque 8 9 ; Function Attrs: nounwind 10 define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { 11 entry: 12 tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !18, metadata !27), !dbg !28 13 tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !19, metadata !27), !dbg !28 14 tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !20, metadata !27), !dbg !28 15 tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 16 %cmp = icmp ult i32 %n, 4, !dbg !29 17 br i1 %cmp, label %return, label %if.end, !dbg !31 18 19 if.end: ; preds = %entry 20 tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 21 br label %return, !dbg !33 22 23 return: ; preds = %if.end, %entry 24 %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] 25 ret i32 %retval.0, !dbg !34 26 } 27 28 ; NOTE: This is checking that the register in the DEBUG_VALUE node is not 29 ; accidentally being marked as KILL. The DBG_VALUE node gets introduced in 30 ; If-Conversion, and gets bundled into the IT block. The Post RA Scheduler 31 ; attempts to schedule the Machine Instr, and tries to tag the register in the 32 ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or 33 ; hopefully, triggering an assert). 34 35 ; CHECK: BUNDLE %ITSTATE<imp-def,dead> 36 ; CHECK: * DBG_VALUE %R1, %noreg, !"u" 37 ; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u" 38 39 declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 40 41 ; Function Attrs: nounwind readnone 42 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 43 44 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 45 attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 46 attributes #2 = { nounwind readnone } 47 attributes #3 = { nounwind } 48 49 !llvm.dbg.cu = !{!0} 50 !llvm.module.flags = !{!22, !23, !24, !25} 51 !llvm.ident = !{!26} 52 53 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) 54 !1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") 55 !2 = !{} 56 !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !17) 57 !5 = !DISubroutineType(types: !6) 58 !6 = !{!7, !8, !11, !12, !16} 59 !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) 60 !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 32, align: 32) 61 !9 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !1, line: 5, baseType: !10) 62 !10 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !1, line: 5, flags: DIFlagFwdDecl) 63 !11 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) 64 !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 32, align: 32) 65 !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14) 66 !14 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !1, line: 2, baseType: !15) 67 !15 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) 68 !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !1, line: 3, baseType: !11) 69 !17 = !{!18, !19, !20, !21} 70 !18 = !DILocalVariable(name: "s", arg: 1, scope: !4, file: !1, line: 9, type: !8) 71 !19 = !DILocalVariable(name: "u", arg: 2, scope: !4, file: !1, line: 9, type: !11) 72 !20 = !DILocalVariable(name: "b", arg: 3, scope: !4, file: !1, line: 9, type: !12) 73 !21 = !DILocalVariable(name: "n", arg: 4, scope: !4, file: !1, line: 9, type: !16) 74 !22 = !{i32 2, !"Dwarf Version", i32 4} 75 !23 = !{i32 2, !"Debug Info Version", i32 3} 76 !24 = !{i32 1, !"wchar_size", i32 4} 77 !25 = !{i32 1, !"min_enum_size", i32 4} 78 !26 = !{!"clang version 3.7.0 (llvm/trunk 237059)"} 79 !27 = !DIExpression() 80 !28 = !DILocation(line: 9, scope: !4) 81 !29 = !DILocation(line: 10, scope: !30) 82 !30 = distinct !DILexicalBlock(scope: !4, file: !1, line: 10) 83 !31 = !DILocation(line: 10, scope: !4) 84 !32 = !DILocation(line: 13, scope: !4) 85 !33 = !DILocation(line: 14, scope: !4) 86 !34 = !DILocation(line: 15, scope: !4) 87 88 ... 89 --- 90 name: f 91 alignment: 1 92 exposesReturnsTwice: false 93 hasInlineAsm: false 94 allVRegsAllocated: true 95 isSSA: false 96 tracksRegLiveness: true 97 tracksSubRegLiveness: false 98 liveins: 99 - { reg: '%r0' } 100 - { reg: '%r1' } 101 - { reg: '%r2' } 102 - { reg: '%r3' } 103 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', 104 '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', 105 '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', 106 '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', 107 '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', 108 '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', 109 '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', 110 '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', 111 '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', 112 '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', 113 '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', 114 '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', 115 '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', 116 '%d11_d12_d13_d14' ] 117 frameInfo: 118 isFrameAddressTaken: false 119 isReturnAddressTaken: false 120 hasStackMap: false 121 hasPatchPoint: false 122 stackSize: 8 123 offsetAdjustment: 0 124 maxAlignment: 4 125 adjustsStack: true 126 hasCalls: true 127 maxCallFrameSize: 0 128 hasOpaqueSPAdjustment: false 129 hasVAStart: false 130 hasMustTailInVarArgFunc: false 131 stack: 132 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } 133 - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } 134 body: | 135 bb.0.entry: 136 liveins: %r0, %r1, %r2, %r3, %lr, %r7 137 138 DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 139 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 140 DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 141 DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 142 t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 143 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 144 %r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0 145 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 146 tBX_RET 3, %cpsr, implicit %r0, debug-location !34 147 %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr 148 frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8 149 frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4 150 frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8 151 DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 152 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 153 DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 154 DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 155 %r1 = tMOVr killed %r2, 14, _, debug-location !32 156 %r2 = tMOVr killed %r3, 14, _, debug-location !32 157 tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 158 %r0 = t2MOVi 0, 14, _, _ 159 %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 160 161 ... 162
