1 # RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o - %s | FileCheck %s 2 # This test ensures that the MIR parser parses the callee saved register mask 3 # correctly and that the MIR parser can infer it as well. 4 5 --- | 6 7 define i32 @compute(i32 %a) #0 { 8 body: 9 %c = mul i32 %a, 11 10 ret i32 %c 11 } 12 13 define i32 @foo(i32 %a) #0 { 14 entry: 15 %b = call i32 @compute(i32 %a) 16 ret i32 %b 17 } 18 19 define i32 @bar(i32 %a) #0 { 20 entry: 21 %b = call i32 @compute(i32 %a) 22 ret i32 %b 23 } 24 25 define i32 @empty(i32 %a) #0 { 26 entry: 27 %b = call i32 @compute(i32 %a) 28 ret i32 %b 29 } 30 31 attributes #0 = { "no-frame-pointer-elim"="false" } 32 33 ... 34 --- 35 # CHECK: name: compute 36 # CHECK: liveins: 37 # CHECK-NEXT: - { reg: '%edi' } 38 # CHECK-NEXT: frameInfo: 39 name: compute 40 liveins: 41 - { reg: '%edi' } 42 frameInfo: 43 stackSize: 8 44 body: | 45 bb.0.body: 46 liveins: %edi 47 48 %eax = IMUL32rri8 %edi, 11, implicit-def %eflags 49 RETQ %eax 50 ... 51 --- 52 name: foo 53 liveins: 54 - { reg: '%edi' } 55 # CHECK: name: foo 56 # CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 57 # CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', 58 # CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', 59 # CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] 60 calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 61 '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', 62 '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', 63 '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] 64 body: | 65 bb.0.entry: 66 liveins: %edi 67 68 PUSH64r %rax, implicit-def %rsp, implicit %rsp 69 CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax 70 %rdx = POP64r implicit-def %rsp, implicit %rsp 71 RETQ %eax 72 ... 73 --- 74 name: bar 75 liveins: 76 - { reg: '%edi' } 77 # Verify that the callee saved register can be inferred from register mask 78 # machine operands: 79 # CHECK: name: bar 80 # CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 81 # CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', 82 # CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', 83 # CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] 84 body: | 85 bb.0.entry: 86 liveins: %edi 87 88 PUSH64r %rax, implicit-def %rsp, implicit %rsp 89 CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax 90 %rdx = POP64r implicit-def %rsp, implicit %rsp 91 RETQ %eax 92 ... 93 --- 94 name: empty 95 liveins: 96 - { reg: '%edi' } 97 # Verify that the callee saved register can be empty. 98 # CHECK: name: empty 99 # CHECK: calleeSavedRegisters: [ ] 100 calleeSavedRegisters: [ ] 101 body: | 102 bb.0.entry: 103 liveins: %edi 104 105 PUSH64r %rax, implicit-def %rsp, implicit %rsp 106 CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax 107 %rdx = POP64r implicit-def %rsp, implicit %rsp 108 RETQ %eax 109 ... 110
