1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ 2 ; RUN: -check-prefixes=ALL,M2,M2-M3 3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ 4 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ 6 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ 8 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ 10 ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ 12 ; RUN: -check-prefixes=ALL,SEL-32,32R6 13 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ 14 ; RUN: -check-prefixes=ALL,M3,M2-M3 15 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ 16 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 17 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ 18 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ 20 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 21 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ 22 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ 24 ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ 26 ; RUN: -check-prefixes=ALL,SEL-64,64R6 27 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ 28 ; RUN: -check-prefixes=ALL,MM32R3 29 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ 30 ; RUN: -check-prefixes=ALL,MM32R6,SEL-32 31 32 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { 33 entry: 34 ; ALL-LABEL: tst_select_i1_float: 35 36 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 37 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] 38 ; M2-M3: nop 39 ; M2: jr $ra 40 ; M2: mtc1 $6, $f0 41 ; M3: mov.s $f13, $f14 42 ; M2-M3: $[[BB0]]: 43 ; M2-M3: jr $ra 44 ; M2: mtc1 $5, $f0 45 ; M3: mov.s $f0, $f13 46 47 ; CMOV-32: mtc1 $6, $f0 48 ; CMOV-32: mtc1 $5, $f1 49 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 50 ; CMOV-32: movn.s $f0, $f1, $[[T0]] 51 52 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] 53 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] 54 ; SEL-32: mtc1 $4, $f0 55 ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] 56 57 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 58 ; CMOV-64: movn.s $f14, $f13, $[[T0]] 59 ; CMOV-64: mov.s $f0, $f14 60 61 ; SEL-64: mtc1 $4, $f0 62 ; SEL-64: sel.s $f0, $f14, $f13 63 64 ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]] 65 ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]] 66 ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 67 ; MM32R3: movn.s $f0, $[[F1]], $[[T0]] 68 69 %r = select i1 %s, float %x, float %y 70 ret float %r 71 } 72 73 define float @tst_select_i1_float_reordered(float %x, float %y, 74 i1 signext %s) { 75 entry: 76 ; ALL-LABEL: tst_select_i1_float_reordered: 77 78 ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 79 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] 80 ; M2-M3: nop 81 ; M2: mov.s $f12, $f14 82 ; M3: mov.s $f12, $f13 83 ; M2-M3: $[[BB0]]: 84 ; M2-M3: jr $ra 85 ; M2-M3: mov.s $f0, $f12 86 87 ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 88 ; CMOV-32: movn.s $f14, $f12, $[[T0]] 89 ; CMOV-32: mov.s $f0, $f14 90 91 ; SEL-32: mtc1 $6, $f0 92 ; SEL-32: sel.s $f0, $f14, $f12 93 94 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 95 ; CMOV-64: movn.s $f13, $f12, $[[T0]] 96 ; CMOV-64: mov.s $f0, $f13 97 98 ; SEL-64: mtc1 $6, $f0 99 ; SEL-64: sel.s $f0, $f13, $f12 100 101 ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1 102 ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]] 103 ; MM32R3: mov.s $f0, $[[F0]] 104 105 %r = select i1 %s, float %x, float %y 106 ret float %r 107 } 108 109 define float @tst_select_fcmp_olt_float(float %x, float %y) { 110 entry: 111 ; ALL-LABEL: tst_select_fcmp_olt_float: 112 113 ; M2: c.olt.s $f12, $f14 114 ; M3: c.olt.s $f12, $f13 115 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] 116 ; M2-M3: nop 117 ; M2: mov.s $f12, $f14 118 ; M3: mov.s $f12, $f13 119 ; M2-M3: $[[BB0]]: 120 ; M2-M3: jr $ra 121 ; M2-M3: mov.s $f0, $f12 122 123 ; CMOV-32: c.olt.s $f12, $f14 124 ; CMOV-32: movt.s $f14, $f12, $fcc0 125 ; CMOV-32: mov.s $f0, $f14 126 127 ; SEL-32: cmp.lt.s $f0, $f12, $f14 128 ; SEL-32: sel.s $f0, $f14, $f12 129 130 ; CMOV-64: c.olt.s $f12, $f13 131 ; CMOV-64: movt.s $f13, $f12, $fcc0 132 ; CMOV-64: mov.s $f0, $f13 133 134 ; SEL-64: cmp.lt.s $f0, $f12, $f13 135 ; SEL-64: sel.s $f0, $f13, $f12 136 137 ; MM32R3: c.olt.s $f12, $f14 138 ; MM32R3: movt.s $f14, $f12, $fcc0 139 ; MM32R3: mov.s $f0, $f14 140 141 %s = fcmp olt float %x, %y 142 %r = select i1 %s, float %x, float %y 143 ret float %r 144 } 145 146 define float @tst_select_fcmp_ole_float(float %x, float %y) { 147 entry: 148 ; ALL-LABEL: tst_select_fcmp_ole_float: 149 150 ; M2: c.ole.s $f12, $f14 151 ; M3: c.ole.s $f12, $f13 152 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] 153 ; M2-M3: nop 154 ; M2: mov.s $f12, $f14 155 ; M3: mov.s $f12, $f13 156 ; M2-M3: $[[BB0]]: 157 ; M2-M3: jr $ra 158 ; M2-M3: mov.s $f0, $f12 159 160 ; CMOV-32: c.ole.s $f12, $f14 161 ; CMOV-32: movt.s $f14, $f12, $fcc0 162 ; CMOV-32: mov.s $f0, $f14 163 164 ; SEL-32: cmp.le.s $f0, $f12, $f14 165 ; SEL-32: sel.s $f0, $f14, $f12 166 167 ; CMOV-64: c.ole.s $f12, $f13 168 ; CMOV-64: movt.s $f13, $f12, $fcc0 169 ; CMOV-64: mov.s $f0, $f13 170 171 ; SEL-64: cmp.le.s $f0, $f12, $f13 172 ; SEL-64: sel.s $f0, $f13, $f12 173 174 ; MM32R3: c.ole.s $f12, $f14 175 ; MM32R3: movt.s $f14, $f12, $fcc0 176 ; MM32R3: mov.s $f0, $f14 177 178 %s = fcmp ole float %x, %y 179 %r = select i1 %s, float %x, float %y 180 ret float %r 181 } 182 183 define float @tst_select_fcmp_ogt_float(float %x, float %y) { 184 entry: 185 ; ALL-LABEL: tst_select_fcmp_ogt_float: 186 187 ; M2: c.ule.s $f12, $f14 188 ; M3: c.ule.s $f12, $f13 189 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 190 ; M2-M3: nop 191 ; M2: mov.s $f12, $f14 192 ; M3: mov.s $f12, $f13 193 ; M2-M3: $[[BB0]]: 194 ; M2-M3: jr $ra 195 ; M2-M3: mov.s $f0, $f12 196 197 ; CMOV-32: c.ule.s $f12, $f14 198 ; CMOV-32: movf.s $f14, $f12, $fcc0 199 ; CMOV-32: mov.s $f0, $f14 200 201 ; SEL-32: cmp.lt.s $f0, $f14, $f12 202 ; SEL-32: sel.s $f0, $f14, $f12 203 204 ; CMOV-64: c.ule.s $f12, $f13 205 ; CMOV-64: movf.s $f13, $f12, $fcc0 206 ; CMOV-64: mov.s $f0, $f13 207 208 ; SEL-64: cmp.lt.s $f0, $f13, $f12 209 ; SEL-64: sel.s $f0, $f13, $f12 210 211 ; MM32R3: c.ule.s $f12, $f14 212 ; MM32R3: movf.s $f14, $f12, $fcc0 213 ; MM32R3: mov.s $f0, $f14 214 215 %s = fcmp ogt float %x, %y 216 %r = select i1 %s, float %x, float %y 217 ret float %r 218 } 219 220 define float @tst_select_fcmp_oge_float(float %x, float %y) { 221 entry: 222 ; ALL-LABEL: tst_select_fcmp_oge_float: 223 224 ; M2: c.ult.s $f12, $f14 225 ; M3: c.ult.s $f12, $f13 226 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 227 ; M2-M3: nop 228 ; M2: mov.s $f12, $f14 229 ; M3: mov.s $f12, $f13 230 ; M2-M3: $[[BB0]]: 231 ; M2-M3: jr $ra 232 ; M2-M3: mov.s $f0, $f12 233 234 ; CMOV-32: c.ult.s $f12, $f14 235 ; CMOV-32: movf.s $f14, $f12, $fcc0 236 ; CMOV-32: mov.s $f0, $f14 237 238 ; SEL-32: cmp.le.s $f0, $f14, $f12 239 ; SEL-32: sel.s $f0, $f14, $f12 240 241 ; CMOV-64: c.ult.s $f12, $f13 242 ; CMOV-64: movf.s $f13, $f12, $fcc0 243 ; CMOV-64: mov.s $f0, $f13 244 245 ; SEL-64: cmp.le.s $f0, $f13, $f12 246 ; SEL-64: sel.s $f0, $f13, $f12 247 248 ; MM32R3: c.ult.s $f12, $f14 249 ; MM32R3: movf.s $f14, $f12, $fcc0 250 ; MM32R3: mov.s $f0, $f14 251 252 %s = fcmp oge float %x, %y 253 %r = select i1 %s, float %x, float %y 254 ret float %r 255 } 256 257 define float @tst_select_fcmp_oeq_float(float %x, float %y) { 258 entry: 259 ; ALL-LABEL: tst_select_fcmp_oeq_float: 260 261 ; M2: c.eq.s $f12, $f14 262 ; M3: c.eq.s $f12, $f13 263 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] 264 ; M2-M3: nop 265 ; M2: mov.s $f12, $f14 266 ; M3: mov.s $f12, $f13 267 ; M2-M3: $[[BB0]]: 268 ; M2-M3: jr $ra 269 ; M2-M3: mov.s $f0, $f12 270 271 ; CMOV-32: c.eq.s $f12, $f14 272 ; CMOV-32: movt.s $f14, $f12, $fcc0 273 ; CMOV-32: mov.s $f0, $f14 274 275 ; SEL-32: cmp.eq.s $f0, $f12, $f14 276 ; SEL-32: sel.s $f0, $f14, $f12 277 278 ; CMOV-64: c.eq.s $f12, $f13 279 ; CMOV-64: movt.s $f13, $f12, $fcc0 280 ; CMOV-64: mov.s $f0, $f13 281 282 ; SEL-64: cmp.eq.s $f0, $f12, $f13 283 ; SEL-64: sel.s $f0, $f13, $f12 284 285 ; MM32R3: c.eq.s $f12, $f14 286 ; MM32R3: movt.s $f14, $f12, $fcc0 287 ; MM32R3: mov.s $f0, $f14 288 289 %s = fcmp oeq float %x, %y 290 %r = select i1 %s, float %x, float %y 291 ret float %r 292 } 293 294 define float @tst_select_fcmp_one_float(float %x, float %y) { 295 entry: 296 ; ALL-LABEL: tst_select_fcmp_one_float: 297 298 ; M2: c.ueq.s $f12, $f14 299 ; M3: c.ueq.s $f12, $f13 300 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 301 ; M2-M3: nop 302 ; M2: mov.s $f12, $f14 303 ; M3: mov.s $f12, $f13 304 ; M2-M3: $[[BB0]]: 305 ; M2-M3: jr $ra 306 ; M2-M3: mov.s $f0, $f12 307 308 ; CMOV-32: c.ueq.s $f12, $f14 309 ; CMOV-32: movf.s $f14, $f12, $fcc0 310 ; CMOV-32: mov.s $f0, $f14 311 312 ; SEL-32: cmp.ueq.s $f0, $f12, $f14 313 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 314 ; SEL-32: not $[[T0]], $[[T0]] 315 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 316 ; SEL-32: sel.s $f0, $f14, $f12 317 318 ; CMOV-64: c.ueq.s $f12, $f13 319 ; CMOV-64: movf.s $f13, $f12, $fcc0 320 ; CMOV-64: mov.s $f0, $f13 321 322 ; SEL-64: cmp.ueq.s $f0, $f12, $f13 323 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 324 ; SEL-64: not $[[T0]], $[[T0]] 325 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 326 ; SEL-64: sel.s $f0, $f13, $f12 327 328 ; MM32R3: c.ueq.s $f12, $f14 329 ; MM32R3: movf.s $f14, $f12, $fcc0 330 ; MM32R3: mov.s $f0, $f14 331 332 %s = fcmp one float %x, %y 333 %r = select i1 %s, float %x, float %y 334 ret float %r 335 } 336
