1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s 2 ; ModuleID = '<stdin>' 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 4 target triple = "x86_64-apple-darwin11.2.0" 5 6 ; During legalization, the vselect mask is 'type legalized' into a 7 ; wider BUILD_VECTOR. This causes the introduction of a new 8 ; sign_extend_inreg in the DAG. 9 ; 10 ; A sign_extend_inreg of a vector of ConstantSDNode or undef can be 11 ; always folded into a simple build_vector. 12 ; 13 ; Make sure that the sign_extend_inreg is simplified and that we 14 ; don't generate psll, psraw and pblendvb from the vselect. 15 16 ; CHECK-LABEL: foo8 17 ; CHECK-NOT: psll 18 ; CHECK-NOT: psraw 19 ; CHECK-NOT: pblendvb 20 ; CHECK: ret 21 define void @foo8(float* nocapture %RET) nounwind { 22 allocas: 23 %resultvec.i = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <8 x i8> <i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100> 24 %uint2float = uitofp <8 x i8> %resultvec.i to <8 x float> 25 %ptr = bitcast float * %RET to <8 x float> * 26 store <8 x float> %uint2float, <8 x float>* %ptr, align 4 27 ret void 28 } 29 30
