1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s 2 3 ; CHECK-LABEL: A: 4 ; CHECK-NOT: vunpck 5 ; CHECK: vinsertf128 $1 6 define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp { 7 entry: 8 %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3> 9 ret <8 x float> %shuffle 10 } 11 12 ; CHECK-LABEL: B: 13 ; CHECK-NOT: vunpck 14 ; CHECK: vinsertf128 $1 15 define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp { 16 entry: 17 %shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 1> 18 ret <4 x double> %shuffle 19 } 20 21 declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone 22 23 declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone 24 25 ; Just check that no crash happens 26 ; CHECK-LABEL: _insert_crash: 27 define void @insert_crash() nounwind { 28 allocas: 29 %v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> 30 %ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1> 31 %vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind 32 %ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind 33 %ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 0 34 %double2float = fptrunc double %ret.i1.i.i464 to float 35 %smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 3 36 %blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32> 37 store <4 x i32> %blendAsInt.i503, <4 x i32>* undef, align 4 38 ret void 39 } 40 41 ;; DAG Combine must remove useless vinsertf128 instructions 42 43 ; CHECK-LABEL: DAGCombineA: 44 ; CHECK-NOT: vinsertf128 $1 45 define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly { 46 %1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 47 %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 48 ret <4 x i32> %2 49 } 50 51 ; CHECK-LABEL: DAGCombineB: 52 ; CHECK: vpaddd %xmm 53 ; CHECK-NOT: vinsertf128 $1 54 ; CHECK: vpaddd %xmm 55 define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly { 56 %1 = add <8 x i32> %v1, %v2 57 %2 = add <8 x i32> %1, %v1 58 ret <8 x i32> %2 59 } 60 61 ; CHECK-LABEL: insert_undef_pd: 62 define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) { 63 ; CHECK: vmovaps %ymm1, %ymm0 64 %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0) 65 ret <4 x double> %res 66 } 67 declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone 68 69 70 ; CHECK-LABEL: insert_undef_ps: 71 define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) { 72 ; CHECK: vmovaps %ymm1, %ymm0 73 %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0) 74 ret <8 x float> %res 75 } 76 declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone 77 78 79 ; CHECK-LABEL: insert_undef_si: 80 define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) { 81 ; CHECK: vmovaps %ymm1, %ymm0 82 %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0) 83 ret <8 x i32> %res 84 } 85 declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone 86 87 ; rdar://10643481 88 ; CHECK-LABEL: vinsertf128_combine: 89 define <8 x float> @vinsertf128_combine(float* nocapture %f) nounwind uwtable readonly ssp { 90 ; CHECK-NOT: vmovaps 91 ; CHECK: vinsertf128 92 entry: 93 %add.ptr = getelementptr inbounds float, float* %f, i64 4 94 %0 = bitcast float* %add.ptr to <4 x float>* 95 %1 = load <4 x float>, <4 x float>* %0, align 16 96 %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1) 97 ret <8 x float> %2 98 } 99 100 ; rdar://11076953 101 ; CHECK-LABEL: vinsertf128_ucombine: 102 define <8 x float> @vinsertf128_ucombine(float* nocapture %f) nounwind uwtable readonly ssp { 103 ; CHECK-NOT: vmovups 104 ; CHECK: vinsertf128 105 entry: 106 %add.ptr = getelementptr inbounds float, float* %f, i64 4 107 %0 = bitcast float* %add.ptr to <4 x float>* 108 %1 = load <4 x float>, <4 x float>* %0, align 8 109 %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1) 110 ret <8 x float> %2 111 } 112
