1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ;RUN: llc -mtriple=x86_64-apple-darwin -mcpu=skx < %s | FileCheck %s 3 4 define i32 @combineTESTM_AND_1(<8 x i64> %a, <8 x i64> %b) { 5 ; CHECK-LABEL: combineTESTM_AND_1: 6 ; CHECK: ## BB#0: 7 ; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k0 8 ; CHECK-NEXT: kmovb %k0, %eax 9 ; CHECK-NEXT: retq 10 %and.i = and <8 x i64> %b, %a 11 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 -1) 12 %conv = zext i8 %test.i to i32 13 ret i32 %conv 14 } 15 16 define i32 @combineTESTM_AND_2(<8 x i64> %a, <8 x i64> %b , i8 %mask) { 17 ; CHECK-LABEL: combineTESTM_AND_2: 18 ; CHECK: ## BB#0: 19 ; CHECK-NEXT: kmovb %edi, %k1 20 ; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k0 {%k1} 21 ; CHECK-NEXT: kmovb %k0, %eax 22 ; CHECK-NEXT: retq 23 %and.i = and <8 x i64> %b, %a 24 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 %mask) 25 %conv = zext i8 %test.i to i32 26 ret i32 %conv 27 } 28 29 define i32 @combineTESTM_AND_mask_3(<8 x i64> %a, <8 x i64>* %bptr , i8 %mask) { 30 ; CHECK-LABEL: combineTESTM_AND_mask_3: 31 ; CHECK: ## BB#0: 32 ; CHECK-NEXT: kmovb %esi, %k1 33 ; CHECK-NEXT: vptestmq (%rdi), %zmm0, %k0 {%k1} 34 ; CHECK-NEXT: kmovb %k0, %eax 35 ; CHECK-NEXT: retq 36 %b = load <8 x i64>, <8 x i64>* %bptr 37 %and.i = and <8 x i64> %a, %b 38 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 %mask) 39 %conv = zext i8 %test.i to i32 40 ret i32 %conv 41 } 42 43 define i32 @combineTESTM_AND_mask_4(<8 x i64> %a, <8 x i64>* %bptr , i8 %mask) { 44 ; CHECK-LABEL: combineTESTM_AND_mask_4: 45 ; CHECK: ## BB#0: 46 ; CHECK-NEXT: kmovb %esi, %k1 47 ; CHECK-NEXT: vptestmq (%rdi), %zmm0, %k0 {%k1} 48 ; CHECK-NEXT: kmovb %k0, %eax 49 ; CHECK-NEXT: retq 50 %b = load <8 x i64>, <8 x i64>* %bptr 51 %and.i = and <8 x i64> %b, %a 52 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 %mask) 53 %conv = zext i8 %test.i to i32 54 ret i32 %conv 55 } 56 57 declare i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64>, <8 x i64>, i8) 58
