1 ; RUN: llc -march=x86-64 -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-bottomup -verify-machineinstrs < %s 2 ; RUN: llc -march=x86-64 -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-topdown -verify-machineinstrs < %s 3 ; REQUIRES: asserts 4 ; 5 ; Test the LiveIntervals::handleMove() function. 6 ; 7 ; Moving the DIV32r instruction exercises the regunit update code because 8 ; %EDX has a live range into the function and is used by the DIV32r. 9 ; 10 ; Here sinking a kill + dead def: 11 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use> 12 ; %vreg4: [48r,144r:0) 0@48r 13 ; --> [48r,180r:0) 0@48r 14 ; DH: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r 15 ; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r 16 ; DL: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r 17 ; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r 18 ; 19 define i32 @f1(i32 %a, i32 %b, i32 %c) nounwind uwtable readnone ssp { 20 entry: 21 %y = add i32 %c, 1 22 %x = udiv i32 %b, %a 23 %add = add nsw i32 %y, %x 24 ret i32 %add 25 } 26 27 ; Same as above, but moving a kill + live def: 28 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use> 29 ; %vreg4: [48r,144r:0) 0@48r 30 ; --> [48r,180r:0) 0@48r 31 ; DH: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r 32 ; --> [0B,16r:0)[128r,180r:2)[180r,184r:1) 0@0B-phi 1@180r 2@128r 33 ; DL: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r 34 ; --> [0B,16r:0)[128r,180r:2)[180r,184r:1) 0@0B-phi 1@180r 2@128r 35 ; 36 define i32 @f2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp { 37 entry: 38 %y = sub i32 %c, %d 39 %x = urem i32 %b, %a 40 %add = add nsw i32 %x, %y 41 ret i32 %add 42 } 43 44 ; Moving a use below the existing kill (%vreg5): 45 ; Moving a tied virtual register def (%vreg11): 46 ; 47 ; 96B -> 120B: %vreg11<def,tied1> = SUB32rr %vreg11<tied0>, %vreg5 48 ; %vreg11: [80r,96r:1)[96r,144r:0) 0@96r 1@80r 49 ; --> [80r,120r:1)[120r,144r:0) 0@120r 1@80r 50 ; %vreg5: [16r,112r:0) 0@16r 51 ; --> [16r,120r:0) 0@16r 52 ; 53 define i32 @f3(i32 %a, i32 %b) nounwind uwtable readnone ssp { 54 entry: 55 %y = sub i32 %a, %b 56 %x = add i32 %a, %b 57 %r = mul i32 %x, %y 58 ret i32 %r 59 } 60 61 ; Move EFLAGS dead def across another def: 62 ; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead> 63 ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208r 1@224r 2@272r 3@160r 4@20r 5@304r 64 ; --> [20r,20d:4)[36r,36d:0)[160r,160d:3)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@36r 1@224r 2@272r 3@160r 4@20r 5@304r 65 ; 66 define i32 @f4(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp { 67 entry: 68 %x = sub i32 %a, %b 69 %y = sub i32 %b, %c 70 %z = sub i32 %c, %d 71 %r1 = udiv i32 %x, %y 72 %r2 = mul i32 %z, %r1 73 ret i32 %r2 74 } 75
