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      1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s
      2 declare {i16, i32} @llvm.x86.rdrand.16()
      3 declare {i32, i32} @llvm.x86.rdrand.32()
      4 declare {i64, i32} @llvm.x86.rdrand.64()
      5 
      6 define i32 @_rdrand16_step(i16* %random_val) {
      7   %call = call {i16, i32} @llvm.x86.rdrand.16()
      8   %randval = extractvalue {i16, i32} %call, 0
      9   store i16 %randval, i16* %random_val
     10   %isvalid = extractvalue {i16, i32} %call, 1
     11   ret i32 %isvalid
     12 ; CHECK-LABEL: _rdrand16_step:
     13 ; CHECK: rdrandw	%ax
     14 ; CHECK: movzwl	%ax, %ecx
     15 ; CHECK: movl	$1, %eax
     16 ; CHECK: cmovael	%ecx, %eax
     17 ; CHECK: movw	%cx, (%r[[A0:di|cx]])
     18 ; CHECK: ret
     19 }
     20 
     21 define i32 @_rdrand32_step(i32* %random_val) {
     22   %call = call {i32, i32} @llvm.x86.rdrand.32()
     23   %randval = extractvalue {i32, i32} %call, 0
     24   store i32 %randval, i32* %random_val
     25   %isvalid = extractvalue {i32, i32} %call, 1
     26   ret i32 %isvalid
     27 ; CHECK-LABEL: _rdrand32_step:
     28 ; CHECK: rdrandl	%e[[T0:[a-z]+]]
     29 ; CHECK: movl	$1, %eax
     30 ; CHECK: cmovael	%e[[T0]], %eax
     31 ; CHECK: movl	%e[[T0]], (%r[[A0]])
     32 ; CHECK: ret
     33 }
     34 
     35 define i32 @_rdrand64_step(i64* %random_val) {
     36   %call = call {i64, i32} @llvm.x86.rdrand.64()
     37   %randval = extractvalue {i64, i32} %call, 0
     38   store i64 %randval, i64* %random_val
     39   %isvalid = extractvalue {i64, i32} %call, 1
     40   ret i32 %isvalid
     41 ; CHECK-LABEL: _rdrand64_step:
     42 ; CHECK: rdrandq	%r[[T1:[a-z]+]]
     43 ; CHECK: movl	$1, %eax
     44 ; CHECK: cmovael	%e[[T1]], %eax
     45 ; CHECK: movq	%r[[T1]], (%r[[A0]])
     46 ; CHECK: ret
     47 }
     48 
     49 ; Check that MachineCSE doesn't eliminate duplicate rdrand instructions.
     50 define i32 @CSE() nounwind {
     51  %rand1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
     52  %v1 = extractvalue { i32, i32 } %rand1, 0
     53  %rand2 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
     54  %v2 = extractvalue { i32, i32 } %rand2, 0
     55  %add = add i32 %v2, %v1
     56  ret i32 %add
     57 ; CHECK-LABEL: CSE:
     58 ; CHECK: rdrandl
     59 ; CHECK: rdrandl
     60 }
     61 
     62 ; Check that MachineLICM doesn't hoist rdrand instructions.
     63 define void @loop(i32* %p, i32 %n) nounwind {
     64 entry:
     65   %tobool1 = icmp eq i32 %n, 0
     66   br i1 %tobool1, label %while.end, label %while.body
     67 
     68 while.body:                                       ; preds = %entry, %while.body
     69   %p.addr.03 = phi i32* [ %incdec.ptr, %while.body ], [ %p, %entry ]
     70   %n.addr.02 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
     71   %dec = add nsw i32 %n.addr.02, -1
     72   %incdec.ptr = getelementptr inbounds i32, i32* %p.addr.03, i64 1
     73   %rand = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
     74   %v1 = extractvalue { i32, i32 } %rand, 0
     75   store i32 %v1, i32* %p.addr.03, align 4
     76   %tobool = icmp eq i32 %dec, 0
     77   br i1 %tobool, label %while.end, label %while.body
     78 
     79 while.end:                                        ; preds = %while.body, %entry
     80   ret void
     81 ; CHECK-LABEL: loop:
     82 ; CHECK-NOT: rdrandl
     83 ; CHECK: This Inner Loop Header: Depth=1
     84 ; CHECK: rdrandl
     85 }
     86