1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s 3 4 define <2 x i64> @test_x86_sse2_psll_dq_bs(<2 x i64> %a0) { 5 ; CHECK-LABEL: test_x86_sse2_psll_dq_bs: 6 ; CHECK: ## BB#0: 7 ; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8] 8 ; CHECK-NEXT: retl 9 %res = call <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1] 10 ret <2 x i64> %res 11 } 12 declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32) nounwind readnone 13 14 15 define <2 x i64> @test_x86_sse2_psrl_dq_bs(<2 x i64> %a0) { 16 ; CHECK-LABEL: test_x86_sse2_psrl_dq_bs: 17 ; CHECK: ## BB#0: 18 ; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero 19 ; CHECK-NEXT: retl 20 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1] 21 ret <2 x i64> %res 22 } 23 declare <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64>, i32) nounwind readnone 24 25 define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) { 26 ; CHECK-LABEL: test_x86_sse2_psll_dq: 27 ; CHECK: ## BB#0: 28 ; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14] 29 ; CHECK-NEXT: retl 30 %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1] 31 ret <2 x i64> %res 32 } 33 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone 34 35 36 define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) { 37 ; CHECK-LABEL: test_x86_sse2_psrl_dq: 38 ; CHECK: ## BB#0: 39 ; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero 40 ; CHECK-NEXT: retl 41 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1] 42 ret <2 x i64> %res 43 } 44 declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone 45 46 47 define <2 x double> @test_x86_sse2_cvtdq2pd(<4 x i32> %a0) { 48 ; CHECK-LABEL: test_x86_sse2_cvtdq2pd: 49 ; CHECK: ## BB#0: 50 ; CHECK-NEXT: cvtdq2pd %xmm0, %xmm0 51 ; CHECK-NEXT: retl 52 %res = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0) ; <<2 x double>> [#uses=1] 53 ret <2 x double> %res 54 } 55 declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone 56 57 58 define <2 x double> @test_x86_sse2_cvtps2pd(<4 x float> %a0) { 59 ; CHECK-LABEL: test_x86_sse2_cvtps2pd: 60 ; CHECK: ## BB#0: 61 ; CHECK-NEXT: cvtps2pd %xmm0, %xmm0 62 ; CHECK-NEXT: retl 63 %res = call <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float> %a0) ; <<2 x double>> [#uses=1] 64 ret <2 x double> %res 65 } 66 declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone 67 68 69 define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) { 70 ; CHECK-LABEL: test_x86_sse2_cvttps2dq: 71 ; CHECK: ## BB#0: 72 ; CHECK-NEXT: cvttps2dq %xmm0, %xmm0 73 ; CHECK-NEXT: retl 74 %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1] 75 ret <4 x i32> %res 76 } 77 declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone 78 79 80 define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) { 81 ; CHECK-LABEL: test_x86_sse2_storel_dq: 82 ; CHECK: ## BB#0: 83 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 84 ; CHECK-NEXT: movlps %xmm0, (%eax) 85 ; CHECK-NEXT: retl 86 call void @llvm.x86.sse2.storel.dq(i8* %a0, <4 x i32> %a1) 87 ret void 88 } 89 declare void @llvm.x86.sse2.storel.dq(i8*, <4 x i32>) nounwind 90 91 92 define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) { 93 ; add operation forces the execution domain. 94 ; CHECK-LABEL: test_x86_sse2_storeu_dq: 95 ; CHECK: ## BB#0: 96 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 97 ; CHECK-NEXT: paddb LCPI8_0, %xmm0 98 ; CHECK-NEXT: movdqu %xmm0, (%eax) 99 ; CHECK-NEXT: retl 100 %a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 101 call void @llvm.x86.sse2.storeu.dq(i8* %a0, <16 x i8> %a2) 102 ret void 103 } 104 declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind 105 106 107 define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) { 108 ; fadd operation forces the execution domain. 109 ; CHECK-LABEL: test_x86_sse2_storeu_pd: 110 ; CHECK: ## BB#0: 111 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 112 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero 113 ; CHECK-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7] 114 ; CHECK-NEXT: addpd %xmm0, %xmm1 115 ; CHECK-NEXT: movupd %xmm1, (%eax) 116 ; CHECK-NEXT: retl 117 %a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000> 118 call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a2) 119 ret void 120 } 121 declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind 122 123 define <4 x i32> @test_x86_sse2_pshuf_d(<4 x i32> %a) { 124 ; CHECK-LABEL: test_x86_sse2_pshuf_d: 125 ; CHECK: ## BB#0: ## %entry 126 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] 127 ; CHECK-NEXT: retl 128 entry: 129 %res = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27) nounwind readnone 130 ret <4 x i32> %res 131 } 132 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8) nounwind readnone 133 134 define <8 x i16> @test_x86_sse2_pshufl_w(<8 x i16> %a) { 135 ; CHECK-LABEL: test_x86_sse2_pshufl_w: 136 ; CHECK: ## BB#0: ## %entry 137 ; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] 138 ; CHECK-NEXT: retl 139 entry: 140 %res = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27) nounwind readnone 141 ret <8 x i16> %res 142 } 143 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8) nounwind readnone 144 145 define <8 x i16> @test_x86_sse2_pshufh_w(<8 x i16> %a) { 146 ; CHECK-LABEL: test_x86_sse2_pshufh_w: 147 ; CHECK: ## BB#0: ## %entry 148 ; CHECK-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] 149 ; CHECK-NEXT: retl 150 entry: 151 %res = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27) nounwind readnone 152 ret <8 x i16> %res 153 } 154 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8) nounwind readnone 155 156 define <16 x i8> @max_epu8(<16 x i8> %a0, <16 x i8> %a1) { 157 ; CHECK-LABEL: max_epu8: 158 ; CHECK: ## BB#0: 159 ; CHECK-NEXT: pmaxub %xmm1, %xmm0 160 ; CHECK-NEXT: retl 161 ; 162 %res = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1) 163 ret <16 x i8> %res 164 } 165 declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone 166 167 define <16 x i8> @min_epu8(<16 x i8> %a0, <16 x i8> %a1) { 168 ; CHECK-LABEL: min_epu8: 169 ; CHECK: ## BB#0: 170 ; CHECK-NEXT: pminub %xmm1, %xmm0 171 ; CHECK-NEXT: retl 172 ; 173 %res = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1) 174 ret <16 x i8> %res 175 } 176 declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone 177 178 define <8 x i16> @max_epi16(<8 x i16> %a0, <8 x i16> %a1) { 179 ; CHECK-LABEL: max_epi16: 180 ; CHECK: ## BB#0: 181 ; CHECK-NEXT: pmaxsw %xmm1, %xmm0 182 ; CHECK-NEXT: retl 183 ; 184 %res = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1) 185 ret <8 x i16> %res 186 } 187 declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone 188 189 define <8 x i16> @min_epi16(<8 x i16> %a0, <8 x i16> %a1) { 190 ; CHECK-LABEL: min_epi16: 191 ; CHECK: ## BB#0: 192 ; CHECK-NEXT: pminsw %xmm1, %xmm0 193 ; CHECK-NEXT: retl 194 ; 195 %res = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1) 196 ret <8 x i16> %res 197 } 198 declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone 199 200
