1 ; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 2 ; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown -O0 | FileCheck --check-prefix=CHECK-O0 %s 3 4 @var = global i32 0 5 6 ; Test how llvm handles return type of {i16, i8}. The return value will be 7 ; passed in %eax and %dl. 8 ; CHECK-LABEL: test: 9 ; CHECK: movl %edi 10 ; CHECK: callq gen 11 ; CHECK: movsbl %dl 12 ; CHECK: addl %{{.*}}, %eax 13 ; CHECK-O0-LABEL: test 14 ; CHECK-O0: movl %edi 15 ; CHECK-O0: callq gen 16 ; CHECK-O0: movswl %ax 17 ; CHECK-O0: movsbl %dl 18 ; CHECK-O0: addl 19 ; CHECK-O0: movw %{{.*}}, %ax 20 define i16 @test(i32 %key) { 21 entry: 22 %key.addr = alloca i32, align 4 23 store i32 %key, i32* %key.addr, align 4 24 %0 = load i32, i32* %key.addr, align 4 25 %call = call swiftcc { i16, i8 } @gen(i32 %0) 26 %v3 = extractvalue { i16, i8 } %call, 0 27 %v1 = sext i16 %v3 to i32 28 %v5 = extractvalue { i16, i8 } %call, 1 29 %v2 = sext i8 %v5 to i32 30 %add = add nsw i32 %v1, %v2 31 %conv = trunc i32 %add to i16 32 ret i16 %conv 33 } 34 35 declare swiftcc { i16, i8 } @gen(i32) 36 37 ; If we can't pass every return value in register, we will pass everything 38 ; in memroy. The caller provides space for the return value and passes 39 ; the address in %rax. The first input argument will be in %rdi. 40 ; CHECK-LABEL: test2: 41 ; CHECK: leaq (%rsp), %rax 42 ; CHECK: callq gen2 43 ; CHECK: movl (%rsp) 44 ; CHECK-DAG: addl 4(%rsp) 45 ; CHECK-DAG: addl 8(%rsp) 46 ; CHECK-DAG: addl 12(%rsp) 47 ; CHECK-DAG: addl 16(%rsp) 48 ; CHECK-O0-LABEL: test2: 49 ; CHECK-O0-DAG: leaq (%rsp), %rax 50 ; CHECK-O0: callq gen2 51 ; CHECK-O0-DAG: movl (%rsp) 52 ; CHECK-O0-DAG: movl 4(%rsp) 53 ; CHECK-O0-DAG: movl 8(%rsp) 54 ; CHECK-O0-DAG: movl 12(%rsp) 55 ; CHECK-O0-DAG: movl 16(%rsp) 56 ; CHECK-O0: addl 57 ; CHECK-O0: addl 58 ; CHECK-O0: addl 59 ; CHECK-O0: addl 60 ; CHECK-O0: movl %{{.*}}, %eax 61 define i32 @test2(i32 %key) #0 { 62 entry: 63 %key.addr = alloca i32, align 4 64 store i32 %key, i32* %key.addr, align 4 65 %0 = load i32, i32* %key.addr, align 4 66 %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0) 67 68 %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0 69 %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1 70 %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2 71 %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3 72 %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4 73 74 %add = add nsw i32 %v3, %v5 75 %add1 = add nsw i32 %add, %v6 76 %add2 = add nsw i32 %add1, %v7 77 %add3 = add nsw i32 %add2, %v8 78 ret i32 %add3 79 } 80 81 ; The address of the return value is passed in %rax. 82 ; On return, we don't keep the address in %rax. 83 ; CHECK-LABEL: gen2: 84 ; CHECK: movl %edi, 16(%rax) 85 ; CHECK: movl %edi, 12(%rax) 86 ; CHECK: movl %edi, 8(%rax) 87 ; CHECK: movl %edi, 4(%rax) 88 ; CHECK: movl %edi, (%rax) 89 ; CHECK-O0-LABEL: gen2: 90 ; CHECK-O0-DAG: movl %edi, 16(%rax) 91 ; CHECK-O0-DAG: movl %edi, 12(%rax) 92 ; CHECK-O0-DAG: movl %edi, 8(%rax) 93 ; CHECK-O0-DAG: movl %edi, 4(%rax) 94 ; CHECK-O0-DAG: movl %edi, (%rax) 95 define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) { 96 %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0 97 %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1 98 %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2 99 %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3 100 %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4 101 ret { i32, i32, i32, i32, i32 } %Z4 102 } 103 104 ; The return value {i32, i32, i32, i32} will be returned via registers %eax, 105 ; %edx, %ecx, %r8d. 106 ; CHECK-LABEL: test3: 107 ; CHECK: callq gen3 108 ; CHECK: addl %edx, %eax 109 ; CHECK: addl %ecx, %eax 110 ; CHECK: addl %r8d, %eax 111 ; CHECK-O0-LABEL: test3: 112 ; CHECK-O0: callq gen3 113 ; CHECK-O0: addl %edx, %eax 114 ; CHECK-O0: addl %ecx, %eax 115 ; CHECK-O0: addl %r8d, %eax 116 define i32 @test3(i32 %key) #0 { 117 entry: 118 %key.addr = alloca i32, align 4 119 store i32 %key, i32* %key.addr, align 4 120 %0 = load i32, i32* %key.addr, align 4 121 %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0) 122 123 %v3 = extractvalue { i32, i32, i32, i32 } %call, 0 124 %v5 = extractvalue { i32, i32, i32, i32 } %call, 1 125 %v6 = extractvalue { i32, i32, i32, i32 } %call, 2 126 %v7 = extractvalue { i32, i32, i32, i32 } %call, 3 127 128 %add = add nsw i32 %v3, %v5 129 %add1 = add nsw i32 %add, %v6 130 %add2 = add nsw i32 %add1, %v7 131 ret i32 %add2 132 } 133 134 declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key) 135 136 ; The return value {float, float, float, float} will be returned via registers 137 ; %xmm0, %xmm1, %xmm2, %xmm3. 138 ; CHECK-LABEL: test4: 139 ; CHECK: callq gen4 140 ; CHECK: addss %xmm1, %xmm0 141 ; CHECK: addss %xmm2, %xmm0 142 ; CHECK: addss %xmm3, %xmm0 143 ; CHECK-O0-LABEL: test4: 144 ; CHECK-O0: callq gen4 145 ; CHECK-O0: addss %xmm1, %xmm0 146 ; CHECK-O0: addss %xmm2, %xmm0 147 ; CHECK-O0: addss %xmm3, %xmm0 148 define float @test4(float %key) #0 { 149 entry: 150 %key.addr = alloca float, align 4 151 store float %key, float* %key.addr, align 4 152 %0 = load float, float* %key.addr, align 4 153 %call = call swiftcc { float, float, float, float } @gen4(float %0) 154 155 %v3 = extractvalue { float, float, float, float } %call, 0 156 %v5 = extractvalue { float, float, float, float } %call, 1 157 %v6 = extractvalue { float, float, float, float } %call, 2 158 %v7 = extractvalue { float, float, float, float } %call, 3 159 160 %add = fadd float %v3, %v5 161 %add1 = fadd float %add, %v6 162 %add2 = fadd float %add1, %v7 163 ret float %add2 164 } 165 166 declare swiftcc { float, float, float, float } @gen4(float %key) 167 168 ; CHECK-LABEL: consume_i1_ret: 169 ; CHECK: callq produce_i1_ret 170 ; CHECK: andb $1, %al 171 ; CHECK: andb $1, %dl 172 ; CHECK: andb $1, %cl 173 ; CHECK: andb $1, %r8b 174 ; CHECK-O0-LABEL: consume_i1_ret: 175 ; CHECK-O0: callq produce_i1_ret 176 ; CHECK-O0: andb $1, %al 177 ; CHECK-O0: andb $1, %dl 178 ; CHECK-O0: andb $1, %cl 179 ; CHECK-O0: andb $1, %r8b 180 define void @consume_i1_ret() { 181 %call = call swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 182 %v3 = extractvalue { i1, i1, i1, i1 } %call, 0 183 %v5 = extractvalue { i1, i1, i1, i1 } %call, 1 184 %v6 = extractvalue { i1, i1, i1, i1 } %call, 2 185 %v7 = extractvalue { i1, i1, i1, i1 } %call, 3 186 %val = zext i1 %v3 to i32 187 store i32 %val, i32* @var 188 %val2 = zext i1 %v5 to i32 189 store i32 %val2, i32* @var 190 %val3 = zext i1 %v6 to i32 191 store i32 %val3, i32* @var 192 %val4 = zext i1 %v7 to i32 193 store i32 %val4, i32* @var 194 ret void 195 } 196 197 declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 198 199 ; CHECK-LABEL: foo: 200 ; CHECK: movq %rdi, (%rax) 201 ; CHECK-O0-LABEL: foo: 202 ; CHECK-O0: movq %rdi, (%rax) 203 define swiftcc void @foo(i64* sret %agg.result, i64 %val) { 204 store i64 %val, i64* %agg.result 205 ret void 206 } 207
