1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 3 4 ; The easy case: a constant power-of-2 divisor. 5 6 define i64 @const_pow_2(i64 %x) { 7 ; CHECK-LABEL: const_pow_2: 8 ; CHECK: # BB#0: 9 ; CHECK-NEXT: andl $31, %edi 10 ; CHECK-NEXT: movq %rdi, %rax 11 ; CHECK-NEXT: retq 12 ; 13 %urem = urem i64 %x, 32 14 ret i64 %urem 15 } 16 17 ; A left-shifted power-of-2 divisor. Use a weird type for wider coverage. 18 19 define i25 @shift_left_pow_2(i25 %x, i25 %y) { 20 ; CHECK-LABEL: shift_left_pow_2: 21 ; CHECK: # BB#0: 22 ; CHECK-NEXT: movl $1, %eax 23 ; CHECK-NEXT: movl %esi, %ecx 24 ; CHECK-NEXT: shll %cl, %eax 25 ; CHECK-NEXT: addl $33554431, %eax # imm = 0x1FFFFFF 26 ; CHECK-NEXT: andl %edi, %eax 27 ; CHECK-NEXT: retq 28 ; 29 %shl = shl i25 1, %y 30 %urem = urem i25 %x, %shl 31 ret i25 %urem 32 } 33 34 ; FIXME: A logically right-shifted sign bit is a power-of-2 or UB. 35 36 define i16 @shift_right_pow_2(i16 %x, i16 %y) { 37 ; CHECK-LABEL: shift_right_pow_2: 38 ; CHECK: # BB#0: 39 ; CHECK-NEXT: movl $32768, %r8d # imm = 0x8000 40 ; CHECK-NEXT: movl %esi, %ecx 41 ; CHECK-NEXT: shrl %cl, %r8d 42 ; CHECK-NEXT: xorl %edx, %edx 43 ; CHECK-NEXT: movl %edi, %eax 44 ; CHECK-NEXT: divw %r8w 45 ; CHECK-NEXT: movl %edx, %eax 46 ; CHECK-NEXT: retq 47 ; 48 %shr = lshr i16 -32768, %y 49 %urem = urem i16 %x, %shr 50 ret i16 %urem 51 } 52 53 ; FIXME: A zero divisor would be UB, so this could be reduced to an 'and' with 3. 54 55 define i8 @and_pow_2(i8 %x, i8 %y) { 56 ; CHECK-LABEL: and_pow_2: 57 ; CHECK: # BB#0: 58 ; CHECK-NEXT: andb $4, %sil 59 ; CHECK-NEXT: movzbl %dil, %eax 60 ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> 61 ; CHECK-NEXT: divb %sil 62 ; CHECK-NEXT: movzbl %ah, %eax # NOREX 63 ; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> 64 ; CHECK-NEXT: retq 65 ; 66 %and = and i8 %y, 4 67 %urem = urem i8 %x, %and 68 ret i8 %urem 69 } 70 71 ; A vector splat constant divisor should get the same treatment as a scalar. 72 73 define <4 x i32> @vec_const_pow_2(<4 x i32> %x) { 74 ; CHECK-LABEL: vec_const_pow_2: 75 ; CHECK: # BB#0: 76 ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 77 ; CHECK-NEXT: retq 78 ; 79 %urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16> 80 ret <4 x i32> %urem 81 } 82 83
