1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41 4 5 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) { 6 ; SSE2-LABEL: test1: 7 ; SSE2: # BB#0: 8 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] 9 ; SSE2-NEXT: movapd %xmm1, %xmm0 10 ; SSE2-NEXT: retq 11 ; 12 ; SSE41-LABEL: test1: 13 ; SSE41: # BB#0: 14 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] 15 ; SSE41-NEXT: retq 16 %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B 17 ret <4 x i32> %select 18 } 19 20 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) { 21 ; SSE2-LABEL: test2: 22 ; SSE2: # BB#0: 23 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] 24 ; SSE2-NEXT: retq 25 ; 26 ; SSE41-LABEL: test2: 27 ; SSE41: # BB#0: 28 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 29 ; SSE41-NEXT: retq 30 %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x i32> %A, <4 x i32> %B 31 ret <4 x i32> %select 32 } 33 34 define <4 x float> @test3(<4 x float> %A, <4 x float> %B) { 35 ; SSE2-LABEL: test3: 36 ; SSE2: # BB#0: 37 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] 38 ; SSE2-NEXT: movapd %xmm1, %xmm0 39 ; SSE2-NEXT: retq 40 ; 41 ; SSE41-LABEL: test3: 42 ; SSE41: # BB#0: 43 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] 44 ; SSE41-NEXT: retq 45 %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x float> %A, <4 x float> %B 46 ret <4 x float> %select 47 } 48 49 define <4 x float> @test4(<4 x float> %A, <4 x float> %B) { 50 ; SSE2-LABEL: test4: 51 ; SSE2: # BB#0: 52 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] 53 ; SSE2-NEXT: retq 54 ; 55 ; SSE41-LABEL: test4: 56 ; SSE41: # BB#0: 57 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1] 58 ; SSE41-NEXT: retq 59 %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x float> %A, <4 x float> %B 60 ret <4 x float> %select 61 } 62
