1 ; RUN: llc -march=x86 -mcpu=generic -mattr=+sse4.2 < %s | FileCheck %s 2 ; RUN: llc -march=x86 -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s 3 4 ; CHECK: movl 5 ; CHECK: paddw 6 ; CHECK: movq 7 8 ; FIXME - if this test cares about scheduling, why isn't it being checked? 9 10 ; Scheduler causes produce a different instruction order 11 ; ATOM: movl 12 ; ATOM: paddw 13 ; ATOM: movq 14 15 ; bitcast a v4i16 to v2i32 16 17 define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind { 18 entry: 19 %dst.addr = alloca <2 x i32>* ; <<2 x i32>**> [#uses=2] 20 %src.addr = alloca <4 x i16>* ; <<4 x i16>**> [#uses=2] 21 %i = alloca i32, align 4 ; <i32*> [#uses=6] 22 store <2 x i32>* %dst, <2 x i32>** %dst.addr 23 store <4 x i16>* %src, <4 x i16>** %src.addr 24 store i32 0, i32* %i 25 br label %forcond 26 27 forcond: ; preds = %forinc, %entry 28 %tmp = load i32, i32* %i ; <i32> [#uses=1] 29 %cmp = icmp slt i32 %tmp, 4 ; <i1> [#uses=1] 30 br i1 %cmp, label %forbody, label %afterfor 31 32 forbody: ; preds = %forcond 33 %tmp1 = load i32, i32* %i ; <i32> [#uses=1] 34 %tmp2 = load <2 x i32>*, <2 x i32>** %dst.addr ; <<2 x i32>*> [#uses=1] 35 %arrayidx = getelementptr <2 x i32>, <2 x i32>* %tmp2, i32 %tmp1 ; <<2 x i32>*> [#uses=1] 36 %tmp3 = load i32, i32* %i ; <i32> [#uses=1] 37 %tmp4 = load <4 x i16>*, <4 x i16>** %src.addr ; <<4 x i16>*> [#uses=1] 38 %arrayidx5 = getelementptr <4 x i16>, <4 x i16>* %tmp4, i32 %tmp3 ; <<4 x i16>*> [#uses=1] 39 %tmp6 = load <4 x i16>, <4 x i16>* %arrayidx5 ; <<4 x i16>> [#uses=1] 40 %add = add <4 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1 > ; <<4 x i16>> [#uses=1] 41 %conv = bitcast <4 x i16> %add to <2 x i32> ; <<2 x i32>> [#uses=1] 42 store <2 x i32> %conv, <2 x i32>* %arrayidx 43 br label %forinc 44 45 forinc: ; preds = %forbody 46 %tmp7 = load i32, i32* %i ; <i32> [#uses=1] 47 %inc = add i32 %tmp7, 1 ; <i32> [#uses=1] 48 store i32 %inc, i32* %i 49 br label %forcond 50 51 afterfor: ; preds = %forcond 52 ret void 53 } 54
