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      1 // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s
      2 
      3 // Check that the assembler can handle the documented syntax for AArch64
      4 
      5 //------------------------------------------------------------------------------
      6 // Instructions across vector registers
      7 //------------------------------------------------------------------------------
      8 
      9         tbl v0.8b, { v1.16b }, v2.8b
     10         tbl v0.8b, { v1.16b, v2.16b }, v2.8b
     11         tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
     12         tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
     13         tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
     14 
     15 // CHECK: tbl	v0.8b, { v1.16b }, v2.8b  // encoding: [0x20,0x00,0x02,0x0e]
     16 // CHECK: tbl	v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e]
     17 // CHECK: tbl	v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x40,0x02,0x0e]
     18 // CHECK: tbl	v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x60,0x02,0x0e]
     19 // CHECK: tbl	v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x63,0x02,0x0e]
     20 
     21         tbl v0.16b, { v1.16b }, v2.16b
     22         tbl v0.16b, { v1.16b, v2.16b }, v2.16b
     23         tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
     24         tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b
     25         tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b
     26 
     27 // CHECK: tbl	v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x00,0x02,0x4e]
     28 // CHECK: tbl	v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x20,0x02,0x4e]
     29 // CHECK: tbl	v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x40,0x02,0x4e]
     30 // CHECK: tbl	v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x60,0x02,0x4e]
     31 // CHECK: tbl	v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x63,0x02,0x4e]
     32 
     33         tbx v0.8b, { v1.16b }, v2.8b
     34         tbx v0.8b, { v1.16b, v2.16b }, v2.8b
     35         tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
     36         tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
     37         tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
     38 
     39 // CHECK: tbx	v0.8b, { v1.16b }, v2.8b  // encoding: [0x20,0x10,0x02,0x0e]
     40 // CHECK: tbx	v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x30,0x02,0x0e]
     41 // CHECK: tbx	v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x50,0x02,0x0e]
     42 // CHECK: tbx	v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x70,0x02,0x0e]
     43 // CHECK: tbx	v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x73,0x02,0x0e]
     44 
     45         tbx v0.16b, { v1.16b }, v2.16b
     46         tbx v0.16b, { v1.16b, v2.16b }, v2.16b
     47         tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
     48         tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b
     49         tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b
     50 
     51 // CHECK: tbx	v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x10,0x02,0x4e]
     52 // CHECK: tbx	v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x30,0x02,0x4e]
     53 // CHECK: tbx	v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x50,0x02,0x4e]
     54 // CHECK: tbx	v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x70,0x02,0x4e]
     55 // CHECK: tbx	v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x73,0x02,0x4e]
     56