1 # RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s 2 # RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 3 4 0x8 0xcc 0x38 0xd5 5 # CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} 6 0x1a 0xc8 0x38 0xd5 7 # CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} 8 0x42 0xcc 0x38 0xd5 9 # CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} 10 0x51 0xc8 0x38 0xd5 11 # CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} 12 0x7d 0xcb 0x38 0xd5 13 # CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} 14 0x24 0xcb 0x3c 0xd5 15 # CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} 16 0x78 0xcb 0x3c 0xd5 17 # CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} 18 0xa9 0xcb 0x3c 0xd5 19 # CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} 20 0x78 0xcc 0x38 0xd5 21 # CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} 22 0x6e 0xc8 0x38 0xd5 23 # CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} 24 0x13 0x46 0x38 0xd5 25 # CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} 26 0x97 0xcc 0x38 0xd5 27 # CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}} 28 0x94 0xcc 0x3e 0xd5 29 # CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}} 30 0xbc 0xcc 0x38 0xd5 31 # CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}} 32 0xb9 0xc9 0x3c 0xd5 33 # CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}} 34 0xa8 0xcc 0x3e 0xd5 35 # CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}} 36 0xd6 0xcc 0x38 0xd5 37 # CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} 38 0xe5 0xcc 0x38 0xd5 39 # CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} 40 0xe7 0xcc 0x3e 0xd5 41 # CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} 42 0x16 0xcd 0x38 0xd5 43 # CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}} 44 0x84 0xc8 0x38 0xd5 45 # CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} 46 0xab 0xc8 0x38 0xd5 47 # CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} 48 0xdb 0xc8 0x38 0xd5 49 # CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} 50 0xf5 0xc8 0x38 0xd5 51 # CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}} 52 0x2 0xc9 0x38 0xd5 53 # CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}} 54 0x35 0xc9 0x38 0xd5 55 # CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}} 56 0x4a 0xc9 0x38 0xd5 57 # CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}} 58 0x7b 0xc9 0x38 0xd5 59 # CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}} 60 0x14 0xc8 0x3c 0xd5 61 # CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}} 62 0x35 0xc8 0x3c 0xd5 63 # CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}} 64 0x45 0xc8 0x3c 0xd5 65 # CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}} 66 0x64 0xc8 0x3c 0xd5 67 # CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}} 68 0xf 0xc9 0x3c 0xd5 69 # CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}} 70 0x2c 0xc9 0x3c 0xd5 71 # CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}} 72 0x5b 0xc9 0x3c 0xd5 73 # CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}} 74 0x74 0xc9 0x3c 0xd5 75 # CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}} 76 0xa 0xcb 0x3c 0xd5 77 # CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} 78 0x5b 0xcb 0x3c 0xd5 79 # CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} 80 0xe6 0xcb 0x3c 0xd5 81 # CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} 82 0x93 0xc9 0x3c 0xd5 83 # CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}} 84 0x3 0xcc 0x3c 0xd5 85 # CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} 86 0x21 0xcc 0x3c 0xd5 87 # CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} 88 0x56 0xcc 0x3c 0xd5 89 # CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} 90 0x75 0xcc 0x3c 0xd5 91 # CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}} 92 0x86 0xcc 0x3c 0xd5 93 # CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}} 94 0xaa 0xcc 0x3c 0xd5 95 # CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}} 96 0xcb 0xcc 0x3c 0xd5 97 # CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}} 98 0xec 0xcc 0x3c 0xd5 99 # CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}} 100 0x0 0xcd 0x3c 0xd5 101 # CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}} 102 0x35 0xcd 0x3c 0xd5 103 # CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}} 104 0x4d 0xcd 0x3c 0xd5 105 # CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}} 106 0x7a 0xcd 0x3c 0xd5 107 # CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}} 108 0x81 0xcd 0x3c 0xd5 109 # CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}} 110 0xa8 0xcd 0x3c 0xd5 111 # CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}} 112 0xc2 0xcd 0x3c 0xd5 113 # CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}} 114 0xe8 0xcd 0x3c 0xd5 115 # CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}} 116 0x3b 0xcc 0x18 0xd5 117 # CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27 118 0x25 0xc8 0x18 0xd5 119 # CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5 120 0x2d 0xcb 0x18 0xd5 121 # CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13 122 0xb5 0xcb 0x18 0xd5 123 # CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21 124 0xd9 0xcb 0x18 0xd5 125 # CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25 126 0xfc 0xcb 0x18 0xd5 127 # CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28 128 0x67 0xcc 0x18 0xd5 129 # CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7 130 0x69 0xc8 0x18 0xd5 131 # CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9 132 0x1d 0x46 0x18 0xd5 133 # CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29 134 0x98 0xcc 0x18 0xd5 135 # CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24 136 0x80 0xcc 0x1e 0xd5 137 # CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0 138 0xa2 0xcc 0x18 0xd5 139 # CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2 140 0xa5 0xc9 0x1c 0xd5 141 # CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5 142 0xaa 0xcc 0x1e 0xd5 143 # CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10 144 0xd6 0xcc 0x18 0xd5 145 # CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 146 0xeb 0xcc 0x18 0xd5 147 # CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 148 0xe8 0xcc 0x1e 0xd5 149 # CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 150 0x4 0xcd 0x18 0xd5 151 # CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4 152 0x9b 0xc8 0x18 0xd5 153 # CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 154 0xa5 0xc8 0x18 0xd5 155 # CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 156 0xd4 0xc8 0x18 0xd5 157 # CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 158 0xe0 0xc8 0x18 0xd5 159 # CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0 160 0x2 0xc9 0x18 0xd5 161 # CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2 162 0x3d 0xc9 0x18 0xd5 163 # CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29 164 0x57 0xc9 0x18 0xd5 165 # CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23 166 0x6b 0xc9 0x18 0xd5 167 # CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11 168 0x2 0xc8 0x1c 0xd5 169 # CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2 170 0x3b 0xc8 0x1c 0xd5 171 # CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27 172 0x47 0xc8 0x1c 0xd5 173 # CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7 174 0x61 0xc8 0x1c 0xd5 175 # CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1 176 0x7 0xc9 0x1c 0xd5 177 # CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7 178 0x2c 0xc9 0x1c 0xd5 179 # CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12 180 0x4e 0xc9 0x1c 0xd5 181 # CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14 182 0x6d 0xc9 0x1c 0xd5 183 # CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13 184 0x1 0xcb 0x1c 0xd5 185 # CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 186 0x4a 0xcb 0x1c 0xd5 187 # CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10 188 0xf8 0xcb 0x1c 0xd5 189 # CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 190 0x9d 0xc9 0x1c 0xd5 191 # CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29 192 0x1a 0xcc 0x1c 0xd5 193 # CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 194 0x29 0xcc 0x1c 0xd5 195 # CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 196 0x52 0xcc 0x1c 0xd5 197 # CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 198 0x7a 0xcc 0x1c 0xd5 199 # CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26 200 0x96 0xcc 0x1c 0xd5 201 # CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22 202 0xba 0xcc 0x1c 0xd5 203 # CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26 204 0xdb 0xcc 0x1c 0xd5 205 # CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27 206 0xe8 0xcc 0x1c 0xd5 207 # CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8 208 0x11 0xcd 0x1c 0xd5 209 # CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17 210 0x33 0xcd 0x1c 0xd5 211 # CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19 212 0x51 0xcd 0x1c 0xd5 213 # CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17 214 0x65 0xcd 0x1c 0xd5 215 # CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5 216 0x9d 0xcd 0x1c 0xd5 217 # CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29 218 0xa2 0xcd 0x1c 0xd5 219 # CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2 220 0xcd 0xcd 0x1c 0xd5 221 # CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13 222 0xfb 0xcd 0x1c 0xd5 223 # CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27 224
