1 ; RUN: opt < %s -cost-model -analyze -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s 2 ; To see the assembly output: llc -mcpu=cortex-a9 < %s | FileCheck --check-prefix=ASM %s 3 ; ASM lines below are only for reference, tests on that direction should go to tests/CodeGen/ARM 4 5 ; ModuleID = 'arm.ll' 6 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" 7 target triple = "armv7--linux-gnueabihf" 8 9 %T216 = type <2 x i16> 10 %T232 = type <2 x i32> 11 %T264 = type <2 x i64> 12 13 %T416 = type <4 x i16> 14 %T432 = type <4 x i32> 15 %T464 = type <4 x i64> 16 17 define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) { 18 ; COST: function 'direct': 19 %v0 = load %T432, %T432* %loadaddr 20 ; ASM: vld1.64 21 %v1 = load %T432, %T432* %loadaddr2 22 ; ASM: vld1.64 23 %r3 = mul %T432 %v0, %v1 24 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32> 25 ; ASM: vmul.i32 26 store %T432 %r3, %T432* %storeaddr 27 ; ASM: vst1.64 28 ret void 29 } 30 31 define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) { 32 ; COST: function 'ups1632': 33 %v0 = load %T416, %T416* %loadaddr 34 ; ASM: vldr 35 %v1 = load %T416, %T416* %loadaddr2 36 ; ASM: vldr 37 %r1 = sext %T416 %v0 to %T432 38 %r2 = sext %T416 %v1 to %T432 39 ; COST: cost of 0 for instruction: {{.*}} sext <4 x i16> {{.*}} to <4 x i32> 40 %r3 = mul %T432 %r1, %r2 41 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32> 42 ; ASM: vmull.s16 43 store %T432 %r3, %T432* %storeaddr 44 ; ASM: vst1.64 45 ret void 46 } 47 48 define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) { 49 ; COST: function 'upu1632': 50 %v0 = load %T416, %T416* %loadaddr 51 ; ASM: vldr 52 %v1 = load %T416, %T416* %loadaddr2 53 ; ASM: vldr 54 %r1 = zext %T416 %v0 to %T432 55 %r2 = zext %T416 %v1 to %T432 56 ; COST: cost of 0 for instruction: {{.*}} zext <4 x i16> {{.*}} to <4 x i32> 57 %r3 = mul %T432 %r1, %r2 58 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32> 59 ; ASM: vmull.u16 60 store %T432 %r3, %T432* %storeaddr 61 ; ASM: vst1.64 62 ret void 63 } 64 65 define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) { 66 ; COST: function 'ups3264': 67 %v0 = load %T232, %T232* %loadaddr 68 ; ASM: vldr 69 %v1 = load %T232, %T232* %loadaddr2 70 ; ASM: vldr 71 %r3 = mul %T232 %v0, %v1 72 ; ASM: vmul.i32 73 ; COST: cost of 1 for instruction: {{.*}} mul <2 x i32> 74 %st = sext %T232 %r3 to %T264 75 ; ASM: vmovl.s32 76 ; COST: cost of 1 for instruction: {{.*}} sext <2 x i32> {{.*}} to <2 x i64> 77 store %T264 %st, %T264* %storeaddr 78 ; ASM: vst1.64 79 ret void 80 } 81 82 define void @upu3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) { 83 ; COST: function 'upu3264': 84 %v0 = load %T232, %T232* %loadaddr 85 ; ASM: vldr 86 %v1 = load %T232, %T232* %loadaddr2 87 ; ASM: vldr 88 %r3 = mul %T232 %v0, %v1 89 ; ASM: vmul.i32 90 ; COST: cost of 1 for instruction: {{.*}} mul <2 x i32> 91 %st = zext %T232 %r3 to %T264 92 ; ASM: vmovl.u32 93 ; COST: cost of 1 for instruction: {{.*}} zext <2 x i32> {{.*}} to <2 x i64> 94 store %T264 %st, %T264* %storeaddr 95 ; ASM: vst1.64 96 ret void 97 } 98 99 define void @dn3216(%T432* %loadaddr, %T432* %loadaddr2, %T416* %storeaddr) { 100 ; COST: function 'dn3216': 101 %v0 = load %T432, %T432* %loadaddr 102 ; ASM: vld1.64 103 %v1 = load %T432, %T432* %loadaddr2 104 ; ASM: vld1.64 105 %r3 = mul %T432 %v0, %v1 106 ; ASM: vmul.i32 107 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32> 108 %st = trunc %T432 %r3 to %T416 109 ; ASM: vmovn.i32 110 ; COST: cost of 1 for instruction: {{.*}} trunc <4 x i32> {{.*}} to <4 x i16> 111 store %T416 %st, %T416* %storeaddr 112 ; ASM: vstr 113 ret void 114 } 115
