1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 25 #define MRM_MAPPING \ 26 MAP(C0, 32) \ 27 MAP(C1, 33) \ 28 MAP(C2, 34) \ 29 MAP(C3, 35) \ 30 MAP(C4, 36) \ 31 MAP(C5, 37) \ 32 MAP(C6, 38) \ 33 MAP(C7, 39) \ 34 MAP(C8, 40) \ 35 MAP(C9, 41) \ 36 MAP(CA, 42) \ 37 MAP(CB, 43) \ 38 MAP(CC, 44) \ 39 MAP(CD, 45) \ 40 MAP(CE, 46) \ 41 MAP(CF, 47) \ 42 MAP(D0, 48) \ 43 MAP(D1, 49) \ 44 MAP(D2, 50) \ 45 MAP(D3, 51) \ 46 MAP(D4, 52) \ 47 MAP(D5, 53) \ 48 MAP(D6, 54) \ 49 MAP(D7, 55) \ 50 MAP(D8, 56) \ 51 MAP(D9, 57) \ 52 MAP(DA, 58) \ 53 MAP(DB, 59) \ 54 MAP(DC, 60) \ 55 MAP(DD, 61) \ 56 MAP(DE, 62) \ 57 MAP(DF, 63) \ 58 MAP(E0, 64) \ 59 MAP(E1, 65) \ 60 MAP(E2, 66) \ 61 MAP(E3, 67) \ 62 MAP(E4, 68) \ 63 MAP(E5, 69) \ 64 MAP(E6, 70) \ 65 MAP(E7, 71) \ 66 MAP(E8, 72) \ 67 MAP(E9, 73) \ 68 MAP(EA, 74) \ 69 MAP(EB, 75) \ 70 MAP(EC, 76) \ 71 MAP(ED, 77) \ 72 MAP(EE, 78) \ 73 MAP(EF, 79) \ 74 MAP(F0, 80) \ 75 MAP(F1, 81) \ 76 MAP(F2, 82) \ 77 MAP(F3, 83) \ 78 MAP(F4, 84) \ 79 MAP(F5, 85) \ 80 MAP(F6, 86) \ 81 MAP(F7, 87) \ 82 MAP(F8, 88) \ 83 MAP(F9, 89) \ 84 MAP(FA, 90) \ 85 MAP(FB, 91) \ 86 MAP(FC, 92) \ 87 MAP(FD, 93) \ 88 MAP(FE, 94) \ 89 MAP(FF, 95) 90 91 // A clone of X86 since we can't depend on something that is generated. 92 namespace X86Local { 93 enum { 94 Pseudo = 0, 95 RawFrm = 1, 96 AddRegFrm = 2, 97 MRMDestReg = 3, 98 MRMDestMem = 4, 99 MRMSrcReg = 5, 100 MRMSrcMem = 6, 101 RawFrmMemOffs = 7, 102 RawFrmSrc = 8, 103 RawFrmDst = 9, 104 RawFrmDstSrc = 10, 105 RawFrmImm8 = 11, 106 RawFrmImm16 = 12, 107 MRMXr = 14, MRMXm = 15, 108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 110 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 111 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 112 #define MAP(from, to) MRM_##from = to, 113 MRM_MAPPING 114 #undef MAP 115 lastMRM 116 }; 117 118 enum { 119 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6 120 }; 121 122 enum { 123 PS = 1, PD = 2, XS = 3, XD = 4 124 }; 125 126 enum { 127 VEX = 1, XOP = 2, EVEX = 3 128 }; 129 130 enum { 131 OpSize16 = 1, OpSize32 = 2 132 }; 133 134 enum { 135 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 136 }; 137 } 138 139 using namespace X86Disassembler; 140 141 /// isRegFormat - Indicates whether a particular form requires the Mod field of 142 /// the ModR/M byte to be 0b11. 143 /// 144 /// @param form - The form of the instruction. 145 /// @return - true if the form implies that Mod must be 0b11, false 146 /// otherwise. 147 static bool isRegFormat(uint8_t form) { 148 return (form == X86Local::MRMDestReg || 149 form == X86Local::MRMSrcReg || 150 form == X86Local::MRMXr || 151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); 152 } 153 154 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 155 /// Useful for switch statements and the like. 156 /// 157 /// @param init - A reference to the BitsInit to be decoded. 158 /// @return - The field, with the first bit in the BitsInit as the lowest 159 /// order bit. 160 static uint8_t byteFromBitsInit(BitsInit &init) { 161 int width = init.getNumBits(); 162 163 assert(width <= 8 && "Field is too large for uint8_t!"); 164 165 int index; 166 uint8_t mask = 0x01; 167 168 uint8_t ret = 0; 169 170 for (index = 0; index < width; index++) { 171 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 172 ret |= mask; 173 174 mask <<= 1; 175 } 176 177 return ret; 178 } 179 180 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 181 /// name of the field. 182 /// 183 /// @param rec - The record from which to extract the value. 184 /// @param name - The name of the field in the record. 185 /// @return - The field, as translated by byteFromBitsInit(). 186 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 187 BitsInit* bits = rec->getValueAsBitsInit(name); 188 return byteFromBitsInit(*bits); 189 } 190 191 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 192 const CodeGenInstruction &insn, 193 InstrUID uid) { 194 UID = uid; 195 196 Rec = insn.TheDef; 197 Name = Rec->getName(); 198 Spec = &tables.specForUID(UID); 199 200 if (!Rec->isSubClassOf("X86Inst")) { 201 ShouldBeEmitted = false; 202 return; 203 } 204 205 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 206 OpMap = byteFromRec(Rec, "OpMapBits"); 207 Opcode = byteFromRec(Rec, "Opcode"); 208 Form = byteFromRec(Rec, "FormBits"); 209 Encoding = byteFromRec(Rec, "OpEncBits"); 210 211 OpSize = byteFromRec(Rec, "OpSizeBits"); 212 AdSize = byteFromRec(Rec, "AdSizeBits"); 213 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 214 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 215 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3"); 216 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 217 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); 218 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 219 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 220 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 221 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 222 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 223 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 224 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 225 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 226 227 Name = Rec->getName(); 228 229 Operands = &insn.Operands.OperandList; 230 231 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 232 233 // Check for 64-bit inst which does not require REX 234 Is32Bit = false; 235 Is64Bit = false; 236 // FIXME: Is there some better way to check for In64BitMode? 237 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 238 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 239 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 240 Predicates[i]->getName().find("In32Bit") != Name.npos) { 241 Is32Bit = true; 242 break; 243 } 244 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 245 Is64Bit = true; 246 break; 247 } 248 } 249 250 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 251 ShouldBeEmitted = false; 252 return; 253 } 254 255 // Special case since there is no attribute class for 64-bit and VEX 256 if (Name == "VMASKMOVDQU64") { 257 ShouldBeEmitted = false; 258 return; 259 } 260 261 ShouldBeEmitted = true; 262 } 263 264 void RecognizableInstr::processInstr(DisassemblerTables &tables, 265 const CodeGenInstruction &insn, 266 InstrUID uid) 267 { 268 // Ignore "asm parser only" instructions. 269 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 270 return; 271 272 RecognizableInstr recogInstr(tables, insn, uid); 273 274 if (recogInstr.shouldBeEmitted()) { 275 recogInstr.emitInstructionSpecifier(); 276 recogInstr.emitDecodePath(tables); 277 } 278 } 279 280 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 281 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 282 (HasEVEX_KZ ? n##_KZ : \ 283 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 284 285 InstructionContext RecognizableInstr::insnContext() const { 286 InstructionContext insnContext; 287 288 if (Encoding == X86Local::EVEX) { 289 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 290 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 291 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 292 } 293 // VEX_L & VEX_W 294 if (HasVEX_LPrefix && HasVEX_WPrefix) { 295 if (OpPrefix == X86Local::PD) 296 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 297 else if (OpPrefix == X86Local::XS) 298 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 299 else if (OpPrefix == X86Local::XD) 300 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 301 else if (OpPrefix == X86Local::PS) 302 insnContext = EVEX_KB(IC_EVEX_L_W); 303 else { 304 errs() << "Instruction does not use a prefix: " << Name << "\n"; 305 llvm_unreachable("Invalid prefix"); 306 } 307 } else if (HasVEX_LPrefix) { 308 // VEX_L 309 if (OpPrefix == X86Local::PD) 310 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 311 else if (OpPrefix == X86Local::XS) 312 insnContext = EVEX_KB(IC_EVEX_L_XS); 313 else if (OpPrefix == X86Local::XD) 314 insnContext = EVEX_KB(IC_EVEX_L_XD); 315 else if (OpPrefix == X86Local::PS) 316 insnContext = EVEX_KB(IC_EVEX_L); 317 else { 318 errs() << "Instruction does not use a prefix: " << Name << "\n"; 319 llvm_unreachable("Invalid prefix"); 320 } 321 } 322 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) { 323 // EVEX_L2 & VEX_W 324 if (OpPrefix == X86Local::PD) 325 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 326 else if (OpPrefix == X86Local::XS) 327 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 328 else if (OpPrefix == X86Local::XD) 329 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 330 else if (OpPrefix == X86Local::PS) 331 insnContext = EVEX_KB(IC_EVEX_L2_W); 332 else { 333 errs() << "Instruction does not use a prefix: " << Name << "\n"; 334 llvm_unreachable("Invalid prefix"); 335 } 336 } else if (HasEVEX_L2Prefix) { 337 // EVEX_L2 338 if (OpPrefix == X86Local::PD) 339 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 340 else if (OpPrefix == X86Local::XD) 341 insnContext = EVEX_KB(IC_EVEX_L2_XD); 342 else if (OpPrefix == X86Local::XS) 343 insnContext = EVEX_KB(IC_EVEX_L2_XS); 344 else if (OpPrefix == X86Local::PS) 345 insnContext = EVEX_KB(IC_EVEX_L2); 346 else { 347 errs() << "Instruction does not use a prefix: " << Name << "\n"; 348 llvm_unreachable("Invalid prefix"); 349 } 350 } 351 else if (HasVEX_WPrefix) { 352 // VEX_W 353 if (OpPrefix == X86Local::PD) 354 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 355 else if (OpPrefix == X86Local::XS) 356 insnContext = EVEX_KB(IC_EVEX_W_XS); 357 else if (OpPrefix == X86Local::XD) 358 insnContext = EVEX_KB(IC_EVEX_W_XD); 359 else if (OpPrefix == X86Local::PS) 360 insnContext = EVEX_KB(IC_EVEX_W); 361 else { 362 errs() << "Instruction does not use a prefix: " << Name << "\n"; 363 llvm_unreachable("Invalid prefix"); 364 } 365 } 366 // No L, no W 367 else if (OpPrefix == X86Local::PD) 368 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 369 else if (OpPrefix == X86Local::XD) 370 insnContext = EVEX_KB(IC_EVEX_XD); 371 else if (OpPrefix == X86Local::XS) 372 insnContext = EVEX_KB(IC_EVEX_XS); 373 else 374 insnContext = EVEX_KB(IC_EVEX); 375 /// eof EVEX 376 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 377 if (HasVEX_LPrefix && HasVEX_WPrefix) { 378 if (OpPrefix == X86Local::PD) 379 insnContext = IC_VEX_L_W_OPSIZE; 380 else if (OpPrefix == X86Local::XS) 381 insnContext = IC_VEX_L_W_XS; 382 else if (OpPrefix == X86Local::XD) 383 insnContext = IC_VEX_L_W_XD; 384 else if (OpPrefix == X86Local::PS) 385 insnContext = IC_VEX_L_W; 386 else { 387 errs() << "Instruction does not use a prefix: " << Name << "\n"; 388 llvm_unreachable("Invalid prefix"); 389 } 390 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 391 insnContext = IC_VEX_L_OPSIZE; 392 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix) 393 insnContext = IC_VEX_W_OPSIZE; 394 else if (OpPrefix == X86Local::PD) 395 insnContext = IC_VEX_OPSIZE; 396 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 397 insnContext = IC_VEX_L_XS; 398 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 399 insnContext = IC_VEX_L_XD; 400 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS) 401 insnContext = IC_VEX_W_XS; 402 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD) 403 insnContext = IC_VEX_W_XD; 404 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS) 405 insnContext = IC_VEX_W; 406 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 407 insnContext = IC_VEX_L; 408 else if (OpPrefix == X86Local::XD) 409 insnContext = IC_VEX_XD; 410 else if (OpPrefix == X86Local::XS) 411 insnContext = IC_VEX_XS; 412 else if (OpPrefix == X86Local::PS) 413 insnContext = IC_VEX; 414 else { 415 errs() << "Instruction does not use a prefix: " << Name << "\n"; 416 llvm_unreachable("Invalid prefix"); 417 } 418 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 419 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 420 insnContext = IC_64BIT_REXW_OPSIZE; 421 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 422 insnContext = IC_64BIT_REXW_ADSIZE; 423 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 424 insnContext = IC_64BIT_XD_OPSIZE; 425 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 426 insnContext = IC_64BIT_XS_OPSIZE; 427 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 428 insnContext = IC_64BIT_OPSIZE_ADSIZE; 429 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 430 insnContext = IC_64BIT_OPSIZE; 431 else if (AdSize == X86Local::AdSize32) 432 insnContext = IC_64BIT_ADSIZE; 433 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 434 insnContext = IC_64BIT_REXW_XS; 435 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 436 insnContext = IC_64BIT_REXW_XD; 437 else if (OpPrefix == X86Local::XD) 438 insnContext = IC_64BIT_XD; 439 else if (OpPrefix == X86Local::XS) 440 insnContext = IC_64BIT_XS; 441 else if (HasREX_WPrefix) 442 insnContext = IC_64BIT_REXW; 443 else 444 insnContext = IC_64BIT; 445 } else { 446 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 447 insnContext = IC_XD_OPSIZE; 448 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 449 insnContext = IC_XS_OPSIZE; 450 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 451 insnContext = IC_OPSIZE_ADSIZE; 452 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 453 insnContext = IC_OPSIZE; 454 else if (AdSize == X86Local::AdSize16) 455 insnContext = IC_ADSIZE; 456 else if (OpPrefix == X86Local::XD) 457 insnContext = IC_XD; 458 else if (OpPrefix == X86Local::XS) 459 insnContext = IC_XS; 460 else 461 insnContext = IC; 462 } 463 464 return insnContext; 465 } 466 467 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 468 // The scaling factor for AVX512 compressed displacement encoding is an 469 // instruction attribute. Adjust the ModRM encoding type to include the 470 // scale for compressed displacement. 471 if (encoding != ENCODING_RM || CD8_Scale == 0) 472 return; 473 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 474 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling"); 475 } 476 477 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 478 unsigned &physicalOperandIndex, 479 unsigned numPhysicalOperands, 480 const unsigned *operandMapping, 481 OperandEncoding (*encodingFromString) 482 (const std::string&, 483 uint8_t OpSize)) { 484 if (optional) { 485 if (physicalOperandIndex >= numPhysicalOperands) 486 return; 487 } else { 488 assert(physicalOperandIndex < numPhysicalOperands); 489 } 490 491 while (operandMapping[operandIndex] != operandIndex) { 492 Spec->operands[operandIndex].encoding = ENCODING_DUP; 493 Spec->operands[operandIndex].type = 494 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 495 ++operandIndex; 496 } 497 498 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 499 500 OperandEncoding encoding = encodingFromString(typeName, OpSize); 501 // Adjust the encoding type for an operand based on the instruction. 502 adjustOperandEncoding(encoding); 503 Spec->operands[operandIndex].encoding = encoding; 504 Spec->operands[operandIndex].type = typeFromString(typeName, 505 HasREX_WPrefix, OpSize); 506 507 ++operandIndex; 508 ++physicalOperandIndex; 509 } 510 511 void RecognizableInstr::emitInstructionSpecifier() { 512 Spec->name = Name; 513 514 Spec->insnContext = insnContext(); 515 516 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 517 518 unsigned numOperands = OperandList.size(); 519 unsigned numPhysicalOperands = 0; 520 521 // operandMapping maps from operands in OperandList to their originals. 522 // If operandMapping[i] != i, then the entry is a duplicate. 523 unsigned operandMapping[X86_MAX_OPERANDS]; 524 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 525 526 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 527 if (!OperandList[operandIndex].Constraints.empty()) { 528 const CGIOperandList::ConstraintInfo &Constraint = 529 OperandList[operandIndex].Constraints[0]; 530 if (Constraint.isTied()) { 531 operandMapping[operandIndex] = operandIndex; 532 operandMapping[Constraint.getTiedOperand()] = operandIndex; 533 } else { 534 ++numPhysicalOperands; 535 operandMapping[operandIndex] = operandIndex; 536 } 537 } else { 538 ++numPhysicalOperands; 539 operandMapping[operandIndex] = operandIndex; 540 } 541 } 542 543 #define HANDLE_OPERAND(class) \ 544 handleOperand(false, \ 545 operandIndex, \ 546 physicalOperandIndex, \ 547 numPhysicalOperands, \ 548 operandMapping, \ 549 class##EncodingFromString); 550 551 #define HANDLE_OPTIONAL(class) \ 552 handleOperand(true, \ 553 operandIndex, \ 554 physicalOperandIndex, \ 555 numPhysicalOperands, \ 556 operandMapping, \ 557 class##EncodingFromString); 558 559 // operandIndex should always be < numOperands 560 unsigned operandIndex = 0; 561 // physicalOperandIndex should always be < numPhysicalOperands 562 unsigned physicalOperandIndex = 0; 563 564 #ifndef NDEBUG 565 // Given the set of prefix bits, how many additional operands does the 566 // instruction have? 567 unsigned additionalOperands = 0; 568 if (HasVEX_4V || HasVEX_4VOp3) 569 ++additionalOperands; 570 if (HasEVEX_K) 571 ++additionalOperands; 572 #endif 573 574 switch (Form) { 575 default: llvm_unreachable("Unhandled form"); 576 case X86Local::RawFrmSrc: 577 HANDLE_OPERAND(relocation); 578 return; 579 case X86Local::RawFrmDst: 580 HANDLE_OPERAND(relocation); 581 return; 582 case X86Local::RawFrmDstSrc: 583 HANDLE_OPERAND(relocation); 584 HANDLE_OPERAND(relocation); 585 return; 586 case X86Local::RawFrm: 587 // Operand 1 (optional) is an address or immediate. 588 assert(numPhysicalOperands <= 1 && 589 "Unexpected number of operands for RawFrm"); 590 HANDLE_OPTIONAL(relocation) 591 break; 592 case X86Local::RawFrmMemOffs: 593 // Operand 1 is an address. 594 HANDLE_OPERAND(relocation); 595 break; 596 case X86Local::AddRegFrm: 597 // Operand 1 is added to the opcode. 598 // Operand 2 (optional) is an address. 599 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 600 "Unexpected number of operands for AddRegFrm"); 601 HANDLE_OPERAND(opcodeModifier) 602 HANDLE_OPTIONAL(relocation) 603 break; 604 case X86Local::MRMDestReg: 605 // Operand 1 is a register operand in the R/M field. 606 // - In AVX512 there may be a mask operand here - 607 // Operand 2 is a register operand in the Reg/Opcode field. 608 // - In AVX, there is a register operand in the VEX.vvvv field here - 609 // Operand 3 (optional) is an immediate. 610 assert(numPhysicalOperands >= 2 + additionalOperands && 611 numPhysicalOperands <= 3 + additionalOperands && 612 "Unexpected number of operands for MRMDestRegFrm"); 613 614 HANDLE_OPERAND(rmRegister) 615 if (HasEVEX_K) 616 HANDLE_OPERAND(writemaskRegister) 617 618 if (HasVEX_4V) 619 // FIXME: In AVX, the register below becomes the one encoded 620 // in ModRMVEX and the one above the one in the VEX.VVVV field 621 HANDLE_OPERAND(vvvvRegister) 622 623 HANDLE_OPERAND(roRegister) 624 HANDLE_OPTIONAL(immediate) 625 break; 626 case X86Local::MRMDestMem: 627 // Operand 1 is a memory operand (possibly SIB-extended) 628 // Operand 2 is a register operand in the Reg/Opcode field. 629 // - In AVX, there is a register operand in the VEX.vvvv field here - 630 // Operand 3 (optional) is an immediate. 631 assert(numPhysicalOperands >= 2 + additionalOperands && 632 numPhysicalOperands <= 3 + additionalOperands && 633 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 634 635 HANDLE_OPERAND(memory) 636 637 if (HasEVEX_K) 638 HANDLE_OPERAND(writemaskRegister) 639 640 if (HasVEX_4V) 641 // FIXME: In AVX, the register below becomes the one encoded 642 // in ModRMVEX and the one above the one in the VEX.VVVV field 643 HANDLE_OPERAND(vvvvRegister) 644 645 HANDLE_OPERAND(roRegister) 646 HANDLE_OPTIONAL(immediate) 647 break; 648 case X86Local::MRMSrcReg: 649 // Operand 1 is a register operand in the Reg/Opcode field. 650 // Operand 2 is a register operand in the R/M field. 651 // - In AVX, there is a register operand in the VEX.vvvv field here - 652 // Operand 3 (optional) is an immediate. 653 // Operand 4 (optional) is an immediate. 654 655 assert(numPhysicalOperands >= 2 + additionalOperands && 656 numPhysicalOperands <= 4 + additionalOperands && 657 "Unexpected number of operands for MRMSrcRegFrm"); 658 659 HANDLE_OPERAND(roRegister) 660 661 if (HasEVEX_K) 662 HANDLE_OPERAND(writemaskRegister) 663 664 if (HasVEX_4V) 665 // FIXME: In AVX, the register below becomes the one encoded 666 // in ModRMVEX and the one above the one in the VEX.VVVV field 667 HANDLE_OPERAND(vvvvRegister) 668 669 if (HasMemOp4Prefix) 670 HANDLE_OPERAND(immediate) 671 672 HANDLE_OPERAND(rmRegister) 673 674 if (HasVEX_4VOp3) 675 HANDLE_OPERAND(vvvvRegister) 676 677 if (!HasMemOp4Prefix) 678 HANDLE_OPTIONAL(immediate) 679 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 680 HANDLE_OPTIONAL(immediate) 681 break; 682 case X86Local::MRMSrcMem: 683 // Operand 1 is a register operand in the Reg/Opcode field. 684 // Operand 2 is a memory operand (possibly SIB-extended) 685 // - In AVX, there is a register operand in the VEX.vvvv field here - 686 // Operand 3 (optional) is an immediate. 687 688 assert(numPhysicalOperands >= 2 + additionalOperands && 689 numPhysicalOperands <= 4 + additionalOperands && 690 "Unexpected number of operands for MRMSrcMemFrm"); 691 692 HANDLE_OPERAND(roRegister) 693 694 if (HasEVEX_K) 695 HANDLE_OPERAND(writemaskRegister) 696 697 if (HasVEX_4V) 698 // FIXME: In AVX, the register below becomes the one encoded 699 // in ModRMVEX and the one above the one in the VEX.VVVV field 700 HANDLE_OPERAND(vvvvRegister) 701 702 if (HasMemOp4Prefix) 703 HANDLE_OPERAND(immediate) 704 705 HANDLE_OPERAND(memory) 706 707 if (HasVEX_4VOp3) 708 HANDLE_OPERAND(vvvvRegister) 709 710 if (!HasMemOp4Prefix) 711 HANDLE_OPTIONAL(immediate) 712 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 713 break; 714 case X86Local::MRMXr: 715 case X86Local::MRM0r: 716 case X86Local::MRM1r: 717 case X86Local::MRM2r: 718 case X86Local::MRM3r: 719 case X86Local::MRM4r: 720 case X86Local::MRM5r: 721 case X86Local::MRM6r: 722 case X86Local::MRM7r: 723 // Operand 1 is a register operand in the R/M field. 724 // Operand 2 (optional) is an immediate or relocation. 725 // Operand 3 (optional) is an immediate. 726 assert(numPhysicalOperands >= 0 + additionalOperands && 727 numPhysicalOperands <= 3 + additionalOperands && 728 "Unexpected number of operands for MRMnr"); 729 730 if (HasVEX_4V) 731 HANDLE_OPERAND(vvvvRegister) 732 733 if (HasEVEX_K) 734 HANDLE_OPERAND(writemaskRegister) 735 HANDLE_OPTIONAL(rmRegister) 736 HANDLE_OPTIONAL(relocation) 737 HANDLE_OPTIONAL(immediate) 738 break; 739 case X86Local::MRMXm: 740 case X86Local::MRM0m: 741 case X86Local::MRM1m: 742 case X86Local::MRM2m: 743 case X86Local::MRM3m: 744 case X86Local::MRM4m: 745 case X86Local::MRM5m: 746 case X86Local::MRM6m: 747 case X86Local::MRM7m: 748 // Operand 1 is a memory operand (possibly SIB-extended) 749 // Operand 2 (optional) is an immediate or relocation. 750 assert(numPhysicalOperands >= 1 + additionalOperands && 751 numPhysicalOperands <= 2 + additionalOperands && 752 "Unexpected number of operands for MRMnm"); 753 754 if (HasVEX_4V) 755 HANDLE_OPERAND(vvvvRegister) 756 if (HasEVEX_K) 757 HANDLE_OPERAND(writemaskRegister) 758 HANDLE_OPERAND(memory) 759 HANDLE_OPTIONAL(relocation) 760 break; 761 case X86Local::RawFrmImm8: 762 // operand 1 is a 16-bit immediate 763 // operand 2 is an 8-bit immediate 764 assert(numPhysicalOperands == 2 && 765 "Unexpected number of operands for X86Local::RawFrmImm8"); 766 HANDLE_OPERAND(immediate) 767 HANDLE_OPERAND(immediate) 768 break; 769 case X86Local::RawFrmImm16: 770 // operand 1 is a 16-bit immediate 771 // operand 2 is a 16-bit immediate 772 HANDLE_OPERAND(immediate) 773 HANDLE_OPERAND(immediate) 774 break; 775 case X86Local::MRM_F8: 776 if (Opcode == 0xc6) { 777 assert(numPhysicalOperands == 1 && 778 "Unexpected number of operands for X86Local::MRM_F8"); 779 HANDLE_OPERAND(immediate) 780 } else if (Opcode == 0xc7) { 781 assert(numPhysicalOperands == 1 && 782 "Unexpected number of operands for X86Local::MRM_F8"); 783 HANDLE_OPERAND(relocation) 784 } 785 break; 786 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: 787 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: 788 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: 789 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1: 790 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6: 791 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9: 792 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC: 793 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF: 794 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2: 795 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5: 796 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA: 797 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED: 798 case X86Local::MRM_EE: case X86Local::MRM_EF: case X86Local::MRM_F0: 799 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: 800 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: 801 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: 802 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: 803 case X86Local::MRM_FE: case X86Local::MRM_FF: 804 // Ignored. 805 break; 806 } 807 808 #undef HANDLE_OPERAND 809 #undef HANDLE_OPTIONAL 810 } 811 812 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 813 // Special cases where the LLVM tables are not complete 814 815 #define MAP(from, to) \ 816 case X86Local::MRM_##from: 817 818 OpcodeType opcodeType = (OpcodeType)-1; 819 820 ModRMFilter* filter = nullptr; 821 uint8_t opcodeToSet = 0; 822 823 switch (OpMap) { 824 default: llvm_unreachable("Invalid map!"); 825 case X86Local::OB: 826 case X86Local::TB: 827 case X86Local::T8: 828 case X86Local::TA: 829 case X86Local::XOP8: 830 case X86Local::XOP9: 831 case X86Local::XOPA: 832 switch (OpMap) { 833 default: llvm_unreachable("Unexpected map!"); 834 case X86Local::OB: opcodeType = ONEBYTE; break; 835 case X86Local::TB: opcodeType = TWOBYTE; break; 836 case X86Local::T8: opcodeType = THREEBYTE_38; break; 837 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 838 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 839 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 840 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 841 } 842 843 switch (Form) { 844 default: 845 filter = new DumbFilter(); 846 break; 847 case X86Local::MRMDestReg: case X86Local::MRMDestMem: 848 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem: 849 case X86Local::MRMXr: case X86Local::MRMXm: 850 filter = new ModFilter(isRegFormat(Form)); 851 break; 852 case X86Local::MRM0r: case X86Local::MRM1r: 853 case X86Local::MRM2r: case X86Local::MRM3r: 854 case X86Local::MRM4r: case X86Local::MRM5r: 855 case X86Local::MRM6r: case X86Local::MRM7r: 856 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 857 break; 858 case X86Local::MRM0m: case X86Local::MRM1m: 859 case X86Local::MRM2m: case X86Local::MRM3m: 860 case X86Local::MRM4m: case X86Local::MRM5m: 861 case X86Local::MRM6m: case X86Local::MRM7m: 862 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 863 break; 864 MRM_MAPPING 865 filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \ 866 break; 867 } // switch (Form) 868 869 opcodeToSet = Opcode; 870 break; 871 } // switch (OpMap) 872 873 unsigned AddressSize = 0; 874 switch (AdSize) { 875 case X86Local::AdSize16: AddressSize = 16; break; 876 case X86Local::AdSize32: AddressSize = 32; break; 877 case X86Local::AdSize64: AddressSize = 64; break; 878 } 879 880 assert(opcodeType != (OpcodeType)-1 && 881 "Opcode type not set"); 882 assert(filter && "Filter not set"); 883 884 if (Form == X86Local::AddRegFrm) { 885 assert(((opcodeToSet & 7) == 0) && 886 "ADDREG_FRM opcode not aligned"); 887 888 uint8_t currentOpcode; 889 890 for (currentOpcode = opcodeToSet; 891 currentOpcode < opcodeToSet + 8; 892 ++currentOpcode) 893 tables.setTableFields(opcodeType, 894 insnContext(), 895 currentOpcode, 896 *filter, 897 UID, Is32Bit, IgnoresVEX_L, AddressSize); 898 } else { 899 tables.setTableFields(opcodeType, 900 insnContext(), 901 opcodeToSet, 902 *filter, 903 UID, Is32Bit, IgnoresVEX_L, AddressSize); 904 } 905 906 delete filter; 907 908 #undef MAP 909 } 910 911 #define TYPE(str, type) if (s == str) return type; 912 OperandType RecognizableInstr::typeFromString(const std::string &s, 913 bool hasREX_WPrefix, 914 uint8_t OpSize) { 915 if(hasREX_WPrefix) { 916 // For instructions with a REX_W prefix, a declared 32-bit register encoding 917 // is special. 918 TYPE("GR32", TYPE_R32) 919 } 920 if(OpSize == X86Local::OpSize16) { 921 // For OpSize16 instructions, a declared 16-bit register or 922 // immediate encoding is special. 923 TYPE("GR16", TYPE_Rv) 924 TYPE("i16imm", TYPE_IMMv) 925 } else if(OpSize == X86Local::OpSize32) { 926 // For OpSize32 instructions, a declared 32-bit register or 927 // immediate encoding is special. 928 TYPE("GR32", TYPE_Rv) 929 } 930 TYPE("i16mem", TYPE_Mv) 931 TYPE("i16imm", TYPE_IMM16) 932 TYPE("i16i8imm", TYPE_IMMv) 933 TYPE("GR16", TYPE_R16) 934 TYPE("i32mem", TYPE_Mv) 935 TYPE("i32imm", TYPE_IMMv) 936 TYPE("i32i8imm", TYPE_IMM32) 937 TYPE("GR32", TYPE_R32) 938 TYPE("GR32orGR64", TYPE_R32) 939 TYPE("i64mem", TYPE_Mv) 940 TYPE("i64i32imm", TYPE_IMM64) 941 TYPE("i64i8imm", TYPE_IMM64) 942 TYPE("GR64", TYPE_R64) 943 TYPE("i8mem", TYPE_M8) 944 TYPE("i8imm", TYPE_IMM8) 945 TYPE("u8imm", TYPE_UIMM8) 946 TYPE("i32u8imm", TYPE_UIMM8) 947 TYPE("GR8", TYPE_R8) 948 TYPE("VR128", TYPE_XMM128) 949 TYPE("VR128X", TYPE_XMM128) 950 TYPE("f128mem", TYPE_M128) 951 TYPE("f256mem", TYPE_M256) 952 TYPE("f512mem", TYPE_M512) 953 TYPE("FR128", TYPE_XMM128) 954 TYPE("FR64", TYPE_XMM64) 955 TYPE("FR64X", TYPE_XMM64) 956 TYPE("f64mem", TYPE_M64FP) 957 TYPE("sdmem", TYPE_M64FP) 958 TYPE("FR32", TYPE_XMM32) 959 TYPE("FR32X", TYPE_XMM32) 960 TYPE("f32mem", TYPE_M32FP) 961 TYPE("ssmem", TYPE_M32FP) 962 TYPE("RST", TYPE_ST) 963 TYPE("i128mem", TYPE_M128) 964 TYPE("i256mem", TYPE_M256) 965 TYPE("i512mem", TYPE_M512) 966 TYPE("i64i32imm_pcrel", TYPE_REL64) 967 TYPE("i16imm_pcrel", TYPE_REL16) 968 TYPE("i32imm_pcrel", TYPE_REL32) 969 TYPE("SSECC", TYPE_IMM3) 970 TYPE("XOPCC", TYPE_IMM3) 971 TYPE("AVXCC", TYPE_IMM5) 972 TYPE("AVX512ICC", TYPE_AVX512ICC) 973 TYPE("AVX512RC", TYPE_IMM32) 974 TYPE("brtarget32", TYPE_RELv) 975 TYPE("brtarget16", TYPE_RELv) 976 TYPE("brtarget8", TYPE_REL8) 977 TYPE("f80mem", TYPE_M80FP) 978 TYPE("lea64_32mem", TYPE_LEA) 979 TYPE("lea64mem", TYPE_LEA) 980 TYPE("VR64", TYPE_MM64) 981 TYPE("i64imm", TYPE_IMMv) 982 TYPE("anymem", TYPE_M) 983 TYPE("opaque32mem", TYPE_M1616) 984 TYPE("opaque48mem", TYPE_M1632) 985 TYPE("opaque80mem", TYPE_M1664) 986 TYPE("opaque512mem", TYPE_M512) 987 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 988 TYPE("DEBUG_REG", TYPE_DEBUGREG) 989 TYPE("CONTROL_REG", TYPE_CONTROLREG) 990 TYPE("srcidx8", TYPE_SRCIDX8) 991 TYPE("srcidx16", TYPE_SRCIDX16) 992 TYPE("srcidx32", TYPE_SRCIDX32) 993 TYPE("srcidx64", TYPE_SRCIDX64) 994 TYPE("dstidx8", TYPE_DSTIDX8) 995 TYPE("dstidx16", TYPE_DSTIDX16) 996 TYPE("dstidx32", TYPE_DSTIDX32) 997 TYPE("dstidx64", TYPE_DSTIDX64) 998 TYPE("offset16_8", TYPE_MOFFS8) 999 TYPE("offset16_16", TYPE_MOFFS16) 1000 TYPE("offset16_32", TYPE_MOFFS32) 1001 TYPE("offset32_8", TYPE_MOFFS8) 1002 TYPE("offset32_16", TYPE_MOFFS16) 1003 TYPE("offset32_32", TYPE_MOFFS32) 1004 TYPE("offset32_64", TYPE_MOFFS64) 1005 TYPE("offset64_8", TYPE_MOFFS8) 1006 TYPE("offset64_16", TYPE_MOFFS16) 1007 TYPE("offset64_32", TYPE_MOFFS32) 1008 TYPE("offset64_64", TYPE_MOFFS64) 1009 TYPE("VR256", TYPE_XMM256) 1010 TYPE("VR256X", TYPE_XMM256) 1011 TYPE("VR512", TYPE_XMM512) 1012 TYPE("VK1", TYPE_VK1) 1013 TYPE("VK1WM", TYPE_VK1) 1014 TYPE("VK2", TYPE_VK2) 1015 TYPE("VK2WM", TYPE_VK2) 1016 TYPE("VK4", TYPE_VK4) 1017 TYPE("VK4WM", TYPE_VK4) 1018 TYPE("VK8", TYPE_VK8) 1019 TYPE("VK8WM", TYPE_VK8) 1020 TYPE("VK16", TYPE_VK16) 1021 TYPE("VK16WM", TYPE_VK16) 1022 TYPE("VK32", TYPE_VK32) 1023 TYPE("VK32WM", TYPE_VK32) 1024 TYPE("VK64", TYPE_VK64) 1025 TYPE("VK64WM", TYPE_VK64) 1026 TYPE("GR32_NOAX", TYPE_Rv) 1027 TYPE("vx64mem", TYPE_M64) 1028 TYPE("vx128mem", TYPE_M128) 1029 TYPE("vx256mem", TYPE_M256) 1030 TYPE("vy128mem", TYPE_M128) 1031 TYPE("vy256mem", TYPE_M256) 1032 TYPE("vx64xmem", TYPE_M64) 1033 TYPE("vx128xmem", TYPE_M128) 1034 TYPE("vx256xmem", TYPE_M256) 1035 TYPE("vy128xmem", TYPE_M128) 1036 TYPE("vy256xmem", TYPE_M256) 1037 TYPE("vy512mem", TYPE_M512) 1038 TYPE("vz512mem", TYPE_M512) 1039 TYPE("BNDR", TYPE_BNDR) 1040 errs() << "Unhandled type string " << s << "\n"; 1041 llvm_unreachable("Unhandled type string"); 1042 } 1043 #undef TYPE 1044 1045 #define ENCODING(str, encoding) if (s == str) return encoding; 1046 OperandEncoding 1047 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1048 uint8_t OpSize) { 1049 if(OpSize != X86Local::OpSize16) { 1050 // For instructions without an OpSize prefix, a declared 16-bit register or 1051 // immediate encoding is special. 1052 ENCODING("i16imm", ENCODING_IW) 1053 } 1054 ENCODING("i32i8imm", ENCODING_IB) 1055 ENCODING("SSECC", ENCODING_IB) 1056 ENCODING("XOPCC", ENCODING_IB) 1057 ENCODING("AVXCC", ENCODING_IB) 1058 ENCODING("AVX512ICC", ENCODING_IB) 1059 ENCODING("AVX512RC", ENCODING_IB) 1060 ENCODING("i16imm", ENCODING_Iv) 1061 ENCODING("i16i8imm", ENCODING_IB) 1062 ENCODING("i32imm", ENCODING_Iv) 1063 ENCODING("i64i32imm", ENCODING_ID) 1064 ENCODING("i64i8imm", ENCODING_IB) 1065 ENCODING("i8imm", ENCODING_IB) 1066 ENCODING("u8imm", ENCODING_IB) 1067 ENCODING("i32u8imm", ENCODING_IB) 1068 // This is not a typo. Instructions like BLENDVPD put 1069 // register IDs in 8-bit immediates nowadays. 1070 ENCODING("FR32", ENCODING_IB) 1071 ENCODING("FR64", ENCODING_IB) 1072 ENCODING("FR128", ENCODING_IB) 1073 ENCODING("VR128", ENCODING_IB) 1074 ENCODING("VR256", ENCODING_IB) 1075 ENCODING("FR32X", ENCODING_IB) 1076 ENCODING("FR64X", ENCODING_IB) 1077 ENCODING("VR128X", ENCODING_IB) 1078 ENCODING("VR256X", ENCODING_IB) 1079 ENCODING("VR512", ENCODING_IB) 1080 errs() << "Unhandled immediate encoding " << s << "\n"; 1081 llvm_unreachable("Unhandled immediate encoding"); 1082 } 1083 1084 OperandEncoding 1085 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1086 uint8_t OpSize) { 1087 ENCODING("RST", ENCODING_FP) 1088 ENCODING("GR16", ENCODING_RM) 1089 ENCODING("GR32", ENCODING_RM) 1090 ENCODING("GR32orGR64", ENCODING_RM) 1091 ENCODING("GR64", ENCODING_RM) 1092 ENCODING("GR8", ENCODING_RM) 1093 ENCODING("VR128", ENCODING_RM) 1094 ENCODING("VR128X", ENCODING_RM) 1095 ENCODING("FR128", ENCODING_RM) 1096 ENCODING("FR64", ENCODING_RM) 1097 ENCODING("FR32", ENCODING_RM) 1098 ENCODING("FR64X", ENCODING_RM) 1099 ENCODING("FR32X", ENCODING_RM) 1100 ENCODING("VR64", ENCODING_RM) 1101 ENCODING("VR256", ENCODING_RM) 1102 ENCODING("VR256X", ENCODING_RM) 1103 ENCODING("VR512", ENCODING_RM) 1104 ENCODING("VK1", ENCODING_RM) 1105 ENCODING("VK2", ENCODING_RM) 1106 ENCODING("VK4", ENCODING_RM) 1107 ENCODING("VK8", ENCODING_RM) 1108 ENCODING("VK16", ENCODING_RM) 1109 ENCODING("VK32", ENCODING_RM) 1110 ENCODING("VK64", ENCODING_RM) 1111 ENCODING("BNDR", ENCODING_RM) 1112 errs() << "Unhandled R/M register encoding " << s << "\n"; 1113 llvm_unreachable("Unhandled R/M register encoding"); 1114 } 1115 1116 OperandEncoding 1117 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1118 uint8_t OpSize) { 1119 ENCODING("GR16", ENCODING_REG) 1120 ENCODING("GR32", ENCODING_REG) 1121 ENCODING("GR32orGR64", ENCODING_REG) 1122 ENCODING("GR64", ENCODING_REG) 1123 ENCODING("GR8", ENCODING_REG) 1124 ENCODING("VR128", ENCODING_REG) 1125 ENCODING("FR128", ENCODING_REG) 1126 ENCODING("FR64", ENCODING_REG) 1127 ENCODING("FR32", ENCODING_REG) 1128 ENCODING("VR64", ENCODING_REG) 1129 ENCODING("SEGMENT_REG", ENCODING_REG) 1130 ENCODING("DEBUG_REG", ENCODING_REG) 1131 ENCODING("CONTROL_REG", ENCODING_REG) 1132 ENCODING("VR256", ENCODING_REG) 1133 ENCODING("VR256X", ENCODING_REG) 1134 ENCODING("VR128X", ENCODING_REG) 1135 ENCODING("FR64X", ENCODING_REG) 1136 ENCODING("FR32X", ENCODING_REG) 1137 ENCODING("VR512", ENCODING_REG) 1138 ENCODING("VK1", ENCODING_REG) 1139 ENCODING("VK2", ENCODING_REG) 1140 ENCODING("VK4", ENCODING_REG) 1141 ENCODING("VK8", ENCODING_REG) 1142 ENCODING("VK16", ENCODING_REG) 1143 ENCODING("VK32", ENCODING_REG) 1144 ENCODING("VK64", ENCODING_REG) 1145 ENCODING("VK1WM", ENCODING_REG) 1146 ENCODING("VK2WM", ENCODING_REG) 1147 ENCODING("VK4WM", ENCODING_REG) 1148 ENCODING("VK8WM", ENCODING_REG) 1149 ENCODING("VK16WM", ENCODING_REG) 1150 ENCODING("VK32WM", ENCODING_REG) 1151 ENCODING("VK64WM", ENCODING_REG) 1152 ENCODING("BNDR", ENCODING_REG) 1153 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1154 llvm_unreachable("Unhandled reg/opcode register encoding"); 1155 } 1156 1157 OperandEncoding 1158 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1159 uint8_t OpSize) { 1160 ENCODING("GR32", ENCODING_VVVV) 1161 ENCODING("GR64", ENCODING_VVVV) 1162 ENCODING("FR32", ENCODING_VVVV) 1163 ENCODING("FR128", ENCODING_VVVV) 1164 ENCODING("FR64", ENCODING_VVVV) 1165 ENCODING("VR128", ENCODING_VVVV) 1166 ENCODING("VR256", ENCODING_VVVV) 1167 ENCODING("FR32X", ENCODING_VVVV) 1168 ENCODING("FR64X", ENCODING_VVVV) 1169 ENCODING("VR128X", ENCODING_VVVV) 1170 ENCODING("VR256X", ENCODING_VVVV) 1171 ENCODING("VR512", ENCODING_VVVV) 1172 ENCODING("VK1", ENCODING_VVVV) 1173 ENCODING("VK2", ENCODING_VVVV) 1174 ENCODING("VK4", ENCODING_VVVV) 1175 ENCODING("VK8", ENCODING_VVVV) 1176 ENCODING("VK16", ENCODING_VVVV) 1177 ENCODING("VK32", ENCODING_VVVV) 1178 ENCODING("VK64", ENCODING_VVVV) 1179 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1180 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1181 } 1182 1183 OperandEncoding 1184 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1185 uint8_t OpSize) { 1186 ENCODING("VK1WM", ENCODING_WRITEMASK) 1187 ENCODING("VK2WM", ENCODING_WRITEMASK) 1188 ENCODING("VK4WM", ENCODING_WRITEMASK) 1189 ENCODING("VK8WM", ENCODING_WRITEMASK) 1190 ENCODING("VK16WM", ENCODING_WRITEMASK) 1191 ENCODING("VK32WM", ENCODING_WRITEMASK) 1192 ENCODING("VK64WM", ENCODING_WRITEMASK) 1193 errs() << "Unhandled mask register encoding " << s << "\n"; 1194 llvm_unreachable("Unhandled mask register encoding"); 1195 } 1196 1197 OperandEncoding 1198 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1199 uint8_t OpSize) { 1200 ENCODING("i16mem", ENCODING_RM) 1201 ENCODING("i32mem", ENCODING_RM) 1202 ENCODING("i64mem", ENCODING_RM) 1203 ENCODING("i8mem", ENCODING_RM) 1204 ENCODING("ssmem", ENCODING_RM) 1205 ENCODING("sdmem", ENCODING_RM) 1206 ENCODING("f128mem", ENCODING_RM) 1207 ENCODING("f256mem", ENCODING_RM) 1208 ENCODING("f512mem", ENCODING_RM) 1209 ENCODING("f64mem", ENCODING_RM) 1210 ENCODING("f32mem", ENCODING_RM) 1211 ENCODING("i128mem", ENCODING_RM) 1212 ENCODING("i256mem", ENCODING_RM) 1213 ENCODING("i512mem", ENCODING_RM) 1214 ENCODING("f80mem", ENCODING_RM) 1215 ENCODING("lea64_32mem", ENCODING_RM) 1216 ENCODING("lea64mem", ENCODING_RM) 1217 ENCODING("anymem", ENCODING_RM) 1218 ENCODING("opaque32mem", ENCODING_RM) 1219 ENCODING("opaque48mem", ENCODING_RM) 1220 ENCODING("opaque80mem", ENCODING_RM) 1221 ENCODING("opaque512mem", ENCODING_RM) 1222 ENCODING("vx64mem", ENCODING_RM) 1223 ENCODING("vx128mem", ENCODING_RM) 1224 ENCODING("vx256mem", ENCODING_RM) 1225 ENCODING("vy128mem", ENCODING_RM) 1226 ENCODING("vy256mem", ENCODING_RM) 1227 ENCODING("vx64xmem", ENCODING_RM) 1228 ENCODING("vx128xmem", ENCODING_RM) 1229 ENCODING("vx256xmem", ENCODING_RM) 1230 ENCODING("vy128xmem", ENCODING_RM) 1231 ENCODING("vy256xmem", ENCODING_RM) 1232 ENCODING("vy512mem", ENCODING_RM) 1233 ENCODING("vz512mem", ENCODING_RM) 1234 errs() << "Unhandled memory encoding " << s << "\n"; 1235 llvm_unreachable("Unhandled memory encoding"); 1236 } 1237 1238 OperandEncoding 1239 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1240 uint8_t OpSize) { 1241 if(OpSize != X86Local::OpSize16) { 1242 // For instructions without an OpSize prefix, a declared 16-bit register or 1243 // immediate encoding is special. 1244 ENCODING("i16imm", ENCODING_IW) 1245 } 1246 ENCODING("i16imm", ENCODING_Iv) 1247 ENCODING("i16i8imm", ENCODING_IB) 1248 ENCODING("i32imm", ENCODING_Iv) 1249 ENCODING("i32i8imm", ENCODING_IB) 1250 ENCODING("i64i32imm", ENCODING_ID) 1251 ENCODING("i64i8imm", ENCODING_IB) 1252 ENCODING("i8imm", ENCODING_IB) 1253 ENCODING("u8imm", ENCODING_IB) 1254 ENCODING("i32u8imm", ENCODING_IB) 1255 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1256 ENCODING("i16imm_pcrel", ENCODING_IW) 1257 ENCODING("i32imm_pcrel", ENCODING_ID) 1258 ENCODING("brtarget32", ENCODING_Iv) 1259 ENCODING("brtarget16", ENCODING_Iv) 1260 ENCODING("brtarget8", ENCODING_IB) 1261 ENCODING("i64imm", ENCODING_IO) 1262 ENCODING("offset16_8", ENCODING_Ia) 1263 ENCODING("offset16_16", ENCODING_Ia) 1264 ENCODING("offset16_32", ENCODING_Ia) 1265 ENCODING("offset32_8", ENCODING_Ia) 1266 ENCODING("offset32_16", ENCODING_Ia) 1267 ENCODING("offset32_32", ENCODING_Ia) 1268 ENCODING("offset32_64", ENCODING_Ia) 1269 ENCODING("offset64_8", ENCODING_Ia) 1270 ENCODING("offset64_16", ENCODING_Ia) 1271 ENCODING("offset64_32", ENCODING_Ia) 1272 ENCODING("offset64_64", ENCODING_Ia) 1273 ENCODING("srcidx8", ENCODING_SI) 1274 ENCODING("srcidx16", ENCODING_SI) 1275 ENCODING("srcidx32", ENCODING_SI) 1276 ENCODING("srcidx64", ENCODING_SI) 1277 ENCODING("dstidx8", ENCODING_DI) 1278 ENCODING("dstidx16", ENCODING_DI) 1279 ENCODING("dstidx32", ENCODING_DI) 1280 ENCODING("dstidx64", ENCODING_DI) 1281 errs() << "Unhandled relocation encoding " << s << "\n"; 1282 llvm_unreachable("Unhandled relocation encoding"); 1283 } 1284 1285 OperandEncoding 1286 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1287 uint8_t OpSize) { 1288 ENCODING("GR32", ENCODING_Rv) 1289 ENCODING("GR64", ENCODING_RO) 1290 ENCODING("GR16", ENCODING_Rv) 1291 ENCODING("GR8", ENCODING_RB) 1292 ENCODING("GR32_NOAX", ENCODING_Rv) 1293 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1294 llvm_unreachable("Unhandled opcode modifier encoding"); 1295 } 1296 #undef ENCODING 1297
