1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb1InstrInfo.h" 15 #include "ARM.h" 16 #include "ARMMachineFunctionInfo.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/PseudoSourceValue.h" 22 #include "llvm/ADT/SmallVector.h" 23 #include "Thumb1InstrInfo.h" 24 25 using namespace llvm; 26 27 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) 28 : ARMBaseInstrInfo(STI), RI(*this, STI) { 29 } 30 31 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { 32 return 0; 33 } 34 35 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 36 MachineBasicBlock::iterator I, DebugLoc DL, 37 unsigned DestReg, unsigned SrcReg, 38 bool KillSrc) const { 39 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 40 .addReg(SrcReg, getKillRegState(KillSrc))); 41 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 42 "Thumb1 can only copy GPR registers"); 43 } 44 45 void Thumb1InstrInfo:: 46 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 47 unsigned SrcReg, bool isKill, int FI, 48 const TargetRegisterClass *RC, 49 const TargetRegisterInfo *TRI) const { 50 assert((RC == ARM::tGPRRegisterClass || 51 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 52 isARMLowRegister(SrcReg))) && "Unknown regclass!"); 53 54 if (RC == ARM::tGPRRegisterClass || 55 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 56 isARMLowRegister(SrcReg))) { 57 DebugLoc DL; 58 if (I != MBB.end()) DL = I->getDebugLoc(); 59 60 MachineFunction &MF = *MBB.getParent(); 61 MachineFrameInfo &MFI = *MF.getFrameInfo(); 62 MachineMemOperand *MMO = 63 MF.getMachineMemOperand( 64 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 65 MachineMemOperand::MOStore, 66 MFI.getObjectSize(FI), 67 MFI.getObjectAlignment(FI)); 68 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 69 .addReg(SrcReg, getKillRegState(isKill)) 70 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 71 } 72 } 73 74 void Thumb1InstrInfo:: 75 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 76 unsigned DestReg, int FI, 77 const TargetRegisterClass *RC, 78 const TargetRegisterInfo *TRI) const { 79 assert((RC == ARM::tGPRRegisterClass || 80 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 81 isARMLowRegister(DestReg))) && "Unknown regclass!"); 82 83 if (RC == ARM::tGPRRegisterClass || 84 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 85 isARMLowRegister(DestReg))) { 86 DebugLoc DL; 87 if (I != MBB.end()) DL = I->getDebugLoc(); 88 89 MachineFunction &MF = *MBB.getParent(); 90 MachineFrameInfo &MFI = *MF.getFrameInfo(); 91 MachineMemOperand *MMO = 92 MF.getMachineMemOperand( 93 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 94 MachineMemOperand::MOLoad, 95 MFI.getObjectSize(FI), 96 MFI.getObjectAlignment(FI)); 97 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 98 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 99 } 100 } 101
