1 //===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Even pipeline: 12 13 def EVEN_UNIT : FuncUnit; // Even execution unit: (PC & 0x7 == 000) 14 def ODD_UNIT : FuncUnit; // Odd execution unit: (PC & 0x7 == 100) 15 16 //===----------------------------------------------------------------------===// 17 // Instruction Itinerary classes used for Cell SPU 18 //===----------------------------------------------------------------------===// 19 20 def LoadStore : InstrItinClass; // ODD_UNIT 21 def BranchHints : InstrItinClass; // ODD_UNIT 22 def BranchResolv : InstrItinClass; // ODD_UNIT 23 def ChanOpSPR : InstrItinClass; // ODD_UNIT 24 def ShuffleOp : InstrItinClass; // ODD_UNIT 25 def SelectOp : InstrItinClass; // ODD_UNIT 26 def GatherOp : InstrItinClass; // ODD_UNIT 27 def LoadNOP : InstrItinClass; // ODD_UNIT 28 def ExecNOP : InstrItinClass; // EVEN_UNIT 29 def SPrecFP : InstrItinClass; // EVEN_UNIT 30 def DPrecFP : InstrItinClass; // EVEN_UNIT 31 def FPInt : InstrItinClass; // EVEN_UNIT (FP<->integer) 32 def ByteOp : InstrItinClass; // EVEN_UNIT 33 def IntegerOp : InstrItinClass; // EVEN_UNIT 34 def IntegerMulDiv: InstrItinClass; // EVEN_UNIT 35 def RotShiftVec : InstrItinClass; // EVEN_UNIT Inter vector 36 def RotShiftQuad : InstrItinClass; // ODD_UNIT Entire quad 37 def ImmLoad : InstrItinClass; // EVEN_UNIT 38 39 /* Note: The itinerary for the Cell SPU is somewhat contrived... */ 40 def SPUItineraries : ProcessorItineraries<[ODD_UNIT, EVEN_UNIT], [], [ 41 InstrItinData<LoadStore , [InstrStage<6, [ODD_UNIT]>]>, 42 InstrItinData<BranchHints , [InstrStage<6, [ODD_UNIT]>]>, 43 InstrItinData<BranchResolv, [InstrStage<4, [ODD_UNIT]>]>, 44 InstrItinData<ChanOpSPR , [InstrStage<6, [ODD_UNIT]>]>, 45 InstrItinData<ShuffleOp , [InstrStage<4, [ODD_UNIT]>]>, 46 InstrItinData<SelectOp , [InstrStage<4, [ODD_UNIT]>]>, 47 InstrItinData<GatherOp , [InstrStage<4, [ODD_UNIT]>]>, 48 InstrItinData<LoadNOP , [InstrStage<1, [ODD_UNIT]>]>, 49 InstrItinData<ExecNOP , [InstrStage<1, [EVEN_UNIT]>]>, 50 InstrItinData<SPrecFP , [InstrStage<6, [EVEN_UNIT]>]>, 51 InstrItinData<DPrecFP , [InstrStage<13, [EVEN_UNIT]>]>, 52 InstrItinData<FPInt , [InstrStage<2, [EVEN_UNIT]>]>, 53 InstrItinData<ByteOp , [InstrStage<4, [EVEN_UNIT]>]>, 54 InstrItinData<IntegerOp , [InstrStage<2, [EVEN_UNIT]>]>, 55 InstrItinData<RotShiftVec , [InstrStage<4, [EVEN_UNIT]>]>, 56 InstrItinData<RotShiftQuad, [InstrStage<4, [ODD_UNIT]>]>, 57 InstrItinData<IntegerMulDiv,[InstrStage<7, [EVEN_UNIT]>]>, 58 InstrItinData<ImmLoad , [InstrStage<2, [EVEN_UNIT]>]> 59 ]>; 60
