1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips64 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Mips Operand, Complex Patterns and Transformations Definitions. 16 //===----------------------------------------------------------------------===// 17 18 // Instruction operand types 19 def shamt_64 : Operand<i64>; 20 21 // Unsigned Operand 22 def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24 } 25 26 // Transformation Function - get Imm - 32. 27 def Subtract32 : SDNodeXForm<imm, [{ 28 return getI32Imm((unsigned)N->getZExtValue() - 32); 29 }]>; 30 31 // imm32_63 predicate - True if imm is in range [32, 63]. 32 def imm32_63 : ImmLeaf<i64, 33 [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}], 34 Subtract32>; 35 36 //===----------------------------------------------------------------------===// 37 // Instructions specific format 38 //===----------------------------------------------------------------------===// 39 // Shifts 40 class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm, 41 SDNode OpNode, PatFrag PF>: 42 FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt, shamt_64:$shamt), 43 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 44 [(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, (i64 PF:$shamt)))], 45 IIAlu> { 46 let rs = _rs; 47 } 48 49 class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm, 50 SDNode OpNode>: 51 FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs, CPU64Regs:$rt), 52 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 53 [(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, CPU64Regs:$rs))], IIAlu> { 54 let shamt = _shamt; 55 } 56 57 // Mul, Div 58 let rd = 0, shamt = 0, Defs = [HI64, LO64] in { 59 let isCommutable = 1 in 60 class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>: 61 FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt), 62 !strconcat(instr_asm, "\t$rs, $rt"), [], itin>; 63 64 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 65 FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt), 66 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 67 [(op CPU64Regs:$rs, CPU64Regs:$rt)], itin>; 68 } 69 70 // Move from Hi/Lo 71 let shamt = 0 in { 72 let rs = 0, rt = 0 in 73 class MoveFromLOHI64<bits<6> func, string instr_asm>: 74 FR<0x00, func, (outs CPU64Regs:$rd), (ins), 75 !strconcat(instr_asm, "\t$rd"), [], IIHiLo>; 76 77 let rt = 0, rd = 0 in 78 class MoveToLOHI64<bits<6> func, string instr_asm>: 79 FR<0x00, func, (outs), (ins CPU64Regs:$rs), 80 !strconcat(instr_asm, "\t$rs"), [], IIHiLo>; 81 } 82 83 // Count Leading Ones/Zeros in Word 84 class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>: 85 FR<0x1c, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs), 86 !strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>, 87 Requires<[HasBitCount]> { 88 let shamt = 0; 89 let rt = rd; 90 } 91 92 //===----------------------------------------------------------------------===// 93 // Instruction definition 94 //===----------------------------------------------------------------------===// 95 96 /// Arithmetic Instructions (ALU Immediate) 97 def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16, 98 CPU64Regs>; 99 def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>; 100 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 101 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; 102 def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>; 103 def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>; 104 105 /// Arithmetic Instructions (3-Operand, R-Type) 106 def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>; 107 def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>; 108 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 109 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; 110 def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>; 111 def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>; 112 def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; 113 def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; 114 115 /// Shift Instructions 116 def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>; 117 def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>; 118 def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>; 119 def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>; 120 def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>; 121 def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>; 122 def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>; 123 def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>; 124 def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>; 125 126 // Rotate Instructions 127 let Predicates = [HasMips64r2] in { 128 def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>; 129 def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr, 130 imm32_63>; 131 def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>; 132 } 133 134 /// Load and Store Instructions 135 /// aligned 136 defm LB64 : LoadM64<0x20, "lb", sextloadi8>; 137 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; 138 defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>; 139 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>; 140 defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>; 141 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>; 142 defm SB64 : StoreM64<0x28, "sb", truncstorei8>; 143 defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>; 144 defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>; 145 defm LD : LoadM64<0x37, "ld", load_a>; 146 defm SD : StoreM64<0x3f, "sd", store_a>; 147 148 /// unaligned 149 defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>; 150 defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>; 151 defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>; 152 defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>; 153 defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>; 154 defm ULD : LoadM64<0x37, "uld", load_u, 1>; 155 defm USD : StoreM64<0x3f, "usd", store_u, 1>; 156 157 /// Jump and Branch Instructions 158 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; 159 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; 160 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; 161 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; 162 def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>; 163 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; 164 165 /// Multiply and Divide Instructions. 166 def DMULT : Mul64<0x1c, "dmult", IIImul>; 167 def DMULTu : Mul64<0x1d, "dmultu", IIImul>; 168 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 169 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 170 171 let Defs = [HI64] in 172 def MTHI64 : MoveToLOHI64<0x11, "mthi">; 173 let Defs = [LO64] in 174 def MTLO64 : MoveToLOHI64<0x13, "mtlo">; 175 176 let Uses = [HI64] in 177 def MFHI64 : MoveFromLOHI64<0x10, "mfhi">; 178 let Uses = [LO64] in 179 def MFLO64 : MoveFromLOHI64<0x12, "mflo">; 180 181 /// Count Leading 182 def DCLZ : CountLeading64<0x24, "dclz", 183 [(set CPU64Regs:$rd, (ctlz CPU64Regs:$rs))]>; 184 def DCLO : CountLeading64<0x25, "dclo", 185 [(set CPU64Regs:$rd, (ctlz (not CPU64Regs:$rs)))]>; 186 187 //===----------------------------------------------------------------------===// 188 // Arbitrary patterns that map to one or more instructions 189 //===----------------------------------------------------------------------===// 190 191 // Small immediates 192 def : Pat<(i64 immSExt16:$in), 193 (DADDiu ZERO_64, imm:$in)>; 194 def : Pat<(i64 immZExt16:$in), 195 (ORi64 ZERO_64, imm:$in)>; 196 197 // zextloadi32_u 198 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>, 199 Requires<[IsN64]>; 200 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>, 201 Requires<[NotN64]>; 202 203 // hi/lo relocs 204 def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>; 205 206 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 207 ZERO_64>; 208 209 // setcc patterns 210 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 211 defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 212 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 213 defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 214 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 215
