1 //===- MipsInstrFormats.td - Mips Instruction Formats ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Describe MIPS instructions format 12 // 13 // CPU INSTRUCTION FORMATS 14 // 15 // opcode - operation code. 16 // rs - src reg. 17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18 // rd - dst reg, only used on 3 regs instr. 19 // shamt - only used on shift instructions, contains the shift amount. 20 // funct - combined with opcode field give us an operation code. 21 // 22 //===----------------------------------------------------------------------===// 23 24 // Format specifies the encoding used by the instruction. This is part of the 25 // ad-hoc solution used to emit machine instruction encodings by our machine 26 // code emitter. 27 class Format<bits<4> val> { 28 bits<4> Value = val; 29 } 30 31 def Pseudo : Format<0>; 32 def FrmR : Format<1>; 33 def FrmI : Format<2>; 34 def FrmJ : Format<3>; 35 def FrmFR : Format<4>; 36 def FrmFI : Format<5>; 37 def FrmOther : Format<6>; // Instruction w/ a custom format 38 39 // Generic Mips Format 40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 41 InstrItinClass itin, Format f>: Instruction 42 { 43 field bits<32> Inst; 44 Format Form = f; 45 46 let Namespace = "Mips"; 47 48 bits<6> Opcode = 0; 49 50 // Top 6 bits are the 'opcode' field 51 let Inst{31-26} = Opcode; 52 53 let OutOperandList = outs; 54 let InOperandList = ins; 55 56 let AsmString = asmstr; 57 let Pattern = pattern; 58 let Itinerary = itin; 59 60 // 61 // Attributes specific to Mips instructions... 62 // 63 bits<4> FormBits = Form.Value; 64 65 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 66 let TSFlags{3-0} = FormBits; 67 } 68 69 // Mips Pseudo Instructions Format 70 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: 71 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> { 72 let isCodeGenOnly = 1; 73 let isPseudo = 1; 74 } 75 76 //===----------------------------------------------------------------------===// 77 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 78 //===----------------------------------------------------------------------===// 79 80 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 81 list<dag> pattern, InstrItinClass itin>: 82 MipsInst<outs, ins, asmstr, pattern, itin, FrmR> 83 { 84 bits<5> rd; 85 bits<5> rs; 86 bits<5> rt; 87 bits<5> shamt; 88 bits<6> funct; 89 90 let Opcode = op; 91 let funct = _funct; 92 93 let Inst{25-21} = rs; 94 let Inst{20-16} = rt; 95 let Inst{15-11} = rd; 96 let Inst{10-6} = shamt; 97 let Inst{5-0} = funct; 98 } 99 100 //===----------------------------------------------------------------------===// 101 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 102 //===----------------------------------------------------------------------===// 103 104 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 105 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmI> 106 { 107 bits<5> rt; 108 bits<5> rs; 109 bits<16> imm16; 110 111 let Opcode = op; 112 113 let Inst{25-21} = rs; 114 let Inst{20-16} = rt; 115 let Inst{15-0} = imm16; 116 } 117 118 class CBranchBase<bits<6> op, dag outs, dag ins, string asmstr, 119 list<dag> pattern, InstrItinClass itin>: 120 MipsInst<outs, ins, asmstr, pattern, itin, FrmI> 121 { 122 bits<5> rs; 123 bits<5> rt; 124 bits<16> imm16; 125 126 let Opcode = op; 127 128 let Inst{25-21} = rs; 129 let Inst{20-16} = rt; 130 let Inst{15-0} = imm16; 131 } 132 133 //===----------------------------------------------------------------------===// 134 // Format J instruction class in Mips : <|opcode|address|> 135 //===----------------------------------------------------------------------===// 136 137 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 138 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmJ> 139 { 140 bits<26> addr; 141 142 let Opcode = op; 143 144 let Inst{25-0} = addr; 145 } 146 147 //===----------------------------------------------------------------------===// 148 // 149 // FLOATING POINT INSTRUCTION FORMATS 150 // 151 // opcode - operation code. 152 // fs - src reg. 153 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 154 // fd - dst reg, only used on 3 regs instr. 155 // fmt - double or single precision. 156 // funct - combined with opcode field give us an operation code. 157 // 158 //===----------------------------------------------------------------------===// 159 160 //===----------------------------------------------------------------------===// 161 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|> 162 //===----------------------------------------------------------------------===// 163 164 class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, 165 string asmstr, list<dag> pattern> : 166 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFR> 167 { 168 bits<5> fd; 169 bits<5> fs; 170 bits<5> ft; 171 bits<5> fmt; 172 bits<6> funct; 173 174 let Opcode = op; 175 let funct = _funct; 176 let fmt = _fmt; 177 178 let Inst{25-21} = fmt; 179 let Inst{20-16} = ft; 180 let Inst{15-11} = fs; 181 let Inst{10-6} = fd; 182 let Inst{5-0} = funct; 183 } 184 185 //===----------------------------------------------------------------------===// 186 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 187 //===----------------------------------------------------------------------===// 188 189 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 190 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 191 { 192 bits<5> ft; 193 bits<5> base; 194 bits<16> imm16; 195 196 let Opcode = op; 197 198 let Inst{25-21} = base; 199 let Inst{20-16} = ft; 200 let Inst{15-0} = imm16; 201 } 202 203 //===----------------------------------------------------------------------===// 204 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|> 205 //===----------------------------------------------------------------------===// 206 207 class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> : 208 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 209 { 210 bits<5> fs; 211 bits<5> ft; 212 bits<4> cc; 213 bits<5> fmt; 214 215 let Opcode = 0x11; 216 let fmt = _fmt; 217 218 let Inst{25-21} = fmt; 219 let Inst{20-16} = ft; 220 let Inst{15-11} = fs; 221 let Inst{10-6} = 0; 222 let Inst{5-4} = 0b11; 223 let Inst{3-0} = cc; 224 } 225 226 227 class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr, 228 list<dag> pattern> : 229 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 230 { 231 bits<5> rd; 232 bits<5> rs; 233 bits<3> cc; 234 bits<1> tf; 235 236 let Opcode = 0; 237 let tf = _tf; 238 239 let Inst{25-21} = rs; 240 let Inst{20-18} = cc; 241 let Inst{17} = 0; 242 let Inst{16} = tf; 243 let Inst{15-11} = rd; 244 let Inst{10-6} = 0; 245 let Inst{5-0} = 1; 246 } 247 248 class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, 249 list<dag> pattern> : 250 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 251 { 252 bits<5> fd; 253 bits<5> fs; 254 bits<3> cc; 255 bits<5> fmt; 256 bits<1> tf; 257 258 let Opcode = 17; 259 let fmt = _fmt; 260 let tf = _tf; 261 262 let Inst{25-21} = fmt; 263 let Inst{20-18} = cc; 264 let Inst{17} = 0; 265 let Inst{16} = tf; 266 let Inst{15-11} = fs; 267 let Inst{10-6} = fd; 268 let Inst{5-0} = 17; 269 } 270 271 // FP unary instructions without patterns. 272 class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr, 273 RegisterClass DstRC, RegisterClass SrcRC> : 274 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 275 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> { 276 let ft = 0; 277 } 278 279 // FP unary instructions with patterns. 280 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr, 281 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> : 282 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), 283 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), 284 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> { 285 let ft = 0; 286 } 287 288 class FFR2P<bits<6> funct, bits<5> fmt, string opstr, 289 string fmtstr, RegisterClass RC, SDNode OpNode> : 290 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft), 291 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"), 292 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>; 293
