1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Mips target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsTargetMachine.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/Support/TargetRegistry.h" 18 using namespace llvm; 19 20 extern "C" void LLVMInitializeMipsTarget() { 21 // Register the target. 22 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget); 23 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget); 24 RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target); 25 RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget); 26 } 27 28 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment 29 // The stack is always 8 byte aligned 30 // On function prologue, the stack is created by decrementing 31 // its pointer. Once decremented, all references are done with positive 32 // offset from the stack/frame pointer, using StackGrowsUp enables 33 // an easier handling. 34 // Using CodeModel::Large enables different CALL behavior. 35 MipsTargetMachine:: 36 MipsTargetMachine(const Target &T, StringRef TT, 37 StringRef CPU, StringRef FS, 38 Reloc::Model RM, CodeModel::Model CM, 39 bool isLittle): 40 LLVMTargetMachine(T, TT, CPU, FS, RM, CM), 41 Subtarget(TT, CPU, FS, isLittle), 42 DataLayout(isLittle ? 43 (Subtarget.isABI_N64() ? 44 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" : 45 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : 46 (Subtarget.isABI_N64() ? 47 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" : 48 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")), 49 InstrInfo(*this), 50 FrameLowering(Subtarget), 51 TLInfo(*this), TSInfo(*this), JITInfo() { 52 } 53 54 MipsebTargetMachine:: 55 MipsebTargetMachine(const Target &T, StringRef TT, 56 StringRef CPU, StringRef FS, 57 Reloc::Model RM, CodeModel::Model CM) : 58 MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {} 59 60 MipselTargetMachine:: 61 MipselTargetMachine(const Target &T, StringRef TT, 62 StringRef CPU, StringRef FS, 63 Reloc::Model RM, CodeModel::Model CM) : 64 MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {} 65 66 Mips64ebTargetMachine:: 67 Mips64ebTargetMachine(const Target &T, StringRef TT, 68 StringRef CPU, StringRef FS, 69 Reloc::Model RM, CodeModel::Model CM) : 70 MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {} 71 72 Mips64elTargetMachine:: 73 Mips64elTargetMachine(const Target &T, StringRef TT, 74 StringRef CPU, StringRef FS, 75 Reloc::Model RM, CodeModel::Model CM) : 76 MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {} 77 78 // Install an instruction selector pass using 79 // the ISelDag to gen Mips code. 80 bool MipsTargetMachine:: 81 addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) 82 { 83 PM.add(createMipsISelDag(*this)); 84 return false; 85 } 86 87 // Implemented by targets that want to run passes immediately before 88 // machine code is emitted. return true if -print-machineinstrs should 89 // print out the code after the passes. 90 bool MipsTargetMachine:: 91 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) 92 { 93 PM.add(createMipsDelaySlotFillerPass(*this)); 94 return true; 95 } 96 97 bool MipsTargetMachine:: 98 addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { 99 // Do not restore $gp if target is Mips64. 100 // In N32/64, $gp is a callee-saved register. 101 if (!Subtarget.hasMips64()) 102 PM.add(createMipsEmitGPRestorePass(*this)); 103 return true; 104 } 105 106 bool MipsTargetMachine:: 107 addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { 108 PM.add(createMipsExpandPseudoPass(*this)); 109 return true; 110 } 111 112 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM, 113 CodeGenOpt::Level OptLevel, 114 JITCodeEmitter &JCE) { 115 // Machine code emitter pass for Mips. 116 PM.add(createMipsJITCodeEmitterPass(*this, JCE)); 117 return false; 118 } 119 120
