1 //===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Sparc implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef SPARCINSTRUCTIONINFO_H 15 #define SPARCINSTRUCTIONINFO_H 16 17 #include "llvm/Target/TargetInstrInfo.h" 18 #include "SparcRegisterInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "SparcGenInstrInfo.inc" 22 23 namespace llvm { 24 25 /// SPII - This namespace holds all of the target specific flags that 26 /// instruction info tracks. 27 /// 28 namespace SPII { 29 enum { 30 Pseudo = (1<<0), 31 Load = (1<<1), 32 Store = (1<<2), 33 DelaySlot = (1<<3) 34 }; 35 } 36 37 class SparcInstrInfo : public SparcGenInstrInfo { 38 const SparcRegisterInfo RI; 39 const SparcSubtarget& Subtarget; 40 public: 41 explicit SparcInstrInfo(SparcSubtarget &ST); 42 43 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 44 /// such, whenever a client has an instance of instruction info, it should 45 /// always be able to get register info as well (through this method). 46 /// 47 virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; } 48 49 /// isLoadFromStackSlot - If the specified machine instruction is a direct 50 /// load from a stack slot, return the virtual or physical register number of 51 /// the destination along with the FrameIndex of the loaded stack slot. If 52 /// not, return 0. This predicate must return 0 if the instruction has 53 /// any side effects other than loading from the stack slot. 54 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 55 int &FrameIndex) const; 56 57 /// isStoreToStackSlot - If the specified machine instruction is a direct 58 /// store to a stack slot, return the virtual or physical register number of 59 /// the source reg along with the FrameIndex of the loaded stack slot. If 60 /// not, return 0. This predicate must return 0 if the instruction has 61 /// any side effects other than storing to the stack slot. 62 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 63 int &FrameIndex) const; 64 65 66 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 67 MachineBasicBlock *&FBB, 68 SmallVectorImpl<MachineOperand> &Cond, 69 bool AllowModify = false) const ; 70 71 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 72 73 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 74 MachineBasicBlock *FBB, 75 const SmallVectorImpl<MachineOperand> &Cond, 76 DebugLoc DL) const; 77 78 virtual void copyPhysReg(MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator I, DebugLoc DL, 80 unsigned DestReg, unsigned SrcReg, 81 bool KillSrc) const; 82 83 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 84 MachineBasicBlock::iterator MBBI, 85 unsigned SrcReg, bool isKill, int FrameIndex, 86 const TargetRegisterClass *RC, 87 const TargetRegisterInfo *TRI) const; 88 89 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 90 MachineBasicBlock::iterator MBBI, 91 unsigned DestReg, int FrameIndex, 92 const TargetRegisterClass *RC, 93 const TargetRegisterInfo *TRI) const; 94 95 unsigned getGlobalBaseReg(MachineFunction *MF) const; 96 }; 97 98 } 99 100 #endif 101
