1 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 2 // 3 // Subtarget Enumeration Source Fragment 4 // 5 // Automatically generated file, do not edit! 6 // 7 //===----------------------------------------------------------------------===// 8 9 10 #ifdef GET_SUBTARGETINFO_ENUM 11 #undef GET_SUBTARGETINFO_ENUM 12 namespace llvm { 13 namespace X86 { 14 enum { 15 Feature3DNow = 1ULL << 0, 16 Feature3DNowA = 1ULL << 1, 17 Feature64Bit = 1ULL << 2, 18 FeatureAES = 1ULL << 3, 19 FeatureAVX = 1ULL << 4, 20 FeatureBMI = 1ULL << 5, 21 FeatureCLMUL = 1ULL << 6, 22 FeatureCMOV = 1ULL << 7, 23 FeatureCMPXCHG16B = 1ULL << 8, 24 FeatureF16C = 1ULL << 9, 25 FeatureFMA3 = 1ULL << 10, 26 FeatureFMA4 = 1ULL << 11, 27 FeatureFastUAMem = 1ULL << 12, 28 FeatureLZCNT = 1ULL << 13, 29 FeatureMMX = 1ULL << 14, 30 FeatureMOVBE = 1ULL << 15, 31 FeaturePOPCNT = 1ULL << 16, 32 FeatureRDRAND = 1ULL << 17, 33 FeatureSSE1 = 1ULL << 18, 34 FeatureSSE2 = 1ULL << 19, 35 FeatureSSE3 = 1ULL << 20, 36 FeatureSSE4A = 1ULL << 21, 37 FeatureSSE41 = 1ULL << 22, 38 FeatureSSE42 = 1ULL << 23, 39 FeatureSSSE3 = 1ULL << 24, 40 FeatureSlowBTMem = 1ULL << 25, 41 FeatureVectorUAMem = 1ULL << 26, 42 Mode64Bit = 1ULL << 27, 43 ModeNaCl = 1ULL << 28 44 }; 45 } 46 } // End llvm namespace 47 #endif // GET_SUBTARGETINFO_ENUM 48 49 50 #ifdef GET_SUBTARGETINFO_MC_DESC 51 #undef GET_SUBTARGETINFO_MC_DESC 52 namespace llvm { 53 // Sorted (by key) array of values for CPU features. 54 llvm::SubtargetFeatureKV X86FeatureKV[] = { 55 { "3dnow", "Enable 3DNow! instructions", X86::Feature3DNow, X86::FeatureMMX }, 56 { "3dnowa", "Enable 3DNow! Athlon instructions", X86::Feature3DNowA, X86::Feature3DNow }, 57 { "64bit", "Support 64-bit instructions", X86::Feature64Bit, X86::FeatureCMOV }, 58 { "64bit-mode", "64-bit mode (x86_64)", X86::Mode64Bit, 0ULL }, 59 { "aes", "Enable AES instructions", X86::FeatureAES, 0ULL }, 60 { "avx", "Enable AVX instructions", X86::FeatureAVX, 0ULL }, 61 { "bmi", "Support BMI instructions", X86::FeatureBMI, 0ULL }, 62 { "clmul", "Enable carry-less multiplication instructions", X86::FeatureCLMUL, 0ULL }, 63 { "cmov", "Enable conditional move instructions", X86::FeatureCMOV, 0ULL }, 64 { "cmpxchg16b", "64-bit with cmpxchg16b", X86::FeatureCMPXCHG16B, X86::Feature64Bit }, 65 { "f16c", "Support 16-bit floating point conversion instructions", X86::FeatureF16C, 0ULL }, 66 { "fast-unaligned-mem", "Fast unaligned memory access", X86::FeatureFastUAMem, 0ULL }, 67 { "fma3", "Enable three-operand fused multiple-add", X86::FeatureFMA3, 0ULL }, 68 { "fma4", "Enable four-operand fused multiple-add", X86::FeatureFMA4, 0ULL }, 69 { "lzcnt", "Support LZCNT instruction", X86::FeatureLZCNT, 0ULL }, 70 { "mmx", "Enable MMX instructions", X86::FeatureMMX, 0ULL }, 71 { "movbe", "Support MOVBE instruction", X86::FeatureMOVBE, 0ULL }, 72 { "nacl-mode", "Native Client mode", X86::ModeNaCl, 0ULL }, 73 { "popcnt", "Support POPCNT instruction", X86::FeaturePOPCNT, 0ULL }, 74 { "rdrand", "Support RDRAND instruction", X86::FeatureRDRAND, 0ULL }, 75 { "slow-bt-mem", "Bit testing of memory is slow", X86::FeatureSlowBTMem, 0ULL }, 76 { "sse", "Enable SSE instructions", X86::FeatureSSE1, X86::FeatureMMX | X86::FeatureCMOV }, 77 { "sse2", "Enable SSE2 instructions", X86::FeatureSSE2, X86::FeatureSSE1 }, 78 { "sse3", "Enable SSE3 instructions", X86::FeatureSSE3, X86::FeatureSSE2 }, 79 { "sse41", "Enable SSE 4.1 instructions", X86::FeatureSSE41, X86::FeatureSSSE3 }, 80 { "sse42", "Enable SSE 4.2 instructions", X86::FeatureSSE42, X86::FeatureSSE41 | X86::FeaturePOPCNT }, 81 { "sse4a", "Support SSE 4a instructions", X86::FeatureSSE4A, X86::FeaturePOPCNT }, 82 { "ssse3", "Enable SSSE3 instructions", X86::FeatureSSSE3, X86::FeatureSSE3 }, 83 { "vector-unaligned-mem", "Allow unaligned memory operands on vector/SIMD instructions", X86::FeatureVectorUAMem, 0ULL } 84 }; 85 86 // Sorted (by key) array of values for CPU subtype. 87 llvm::SubtargetFeatureKV X86SubTypeKV[] = { 88 { "amdfam10", "Select the amdfam10 processor", X86::FeatureSSE3 | X86::FeatureSSE4A | X86::Feature3DNowA | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 89 { "athlon", "Select the athlon processor", X86::Feature3DNowA | X86::FeatureSlowBTMem, 0ULL }, 90 { "athlon-4", "Select the athlon-4 processor", X86::FeatureSSE1 | X86::Feature3DNowA | X86::FeatureSlowBTMem, 0ULL }, 91 { "athlon-fx", "Select the athlon-fx processor", X86::FeatureSSE2 | X86::Feature3DNowA | X86::Feature64Bit | X86::FeatureSlowBTMem, 0ULL }, 92 { "athlon-mp", "Select the athlon-mp processor", X86::FeatureSSE1 | X86::Feature3DNowA | X86::FeatureSlowBTMem, 0ULL }, 93 { "athlon-tbird", "Select the athlon-tbird processor", X86::Feature3DNowA | X86::FeatureSlowBTMem, 0ULL }, 94 { "athlon-xp", "Select the athlon-xp processor", X86::FeatureSSE1 | X86::Feature3DNowA | X86::FeatureSlowBTMem, 0ULL }, 95 { "athlon64", "Select the athlon64 processor", X86::FeatureSSE2 | X86::Feature3DNowA | X86::Feature64Bit | X86::FeatureSlowBTMem, 0ULL }, 96 { "athlon64-sse3", "Select the athlon64-sse3 processor", X86::FeatureSSE3 | X86::Feature3DNowA | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 97 { "atom", "Select the atom processor", X86::FeatureSSE3 | X86::FeatureCMPXCHG16B | X86::FeatureMOVBE | X86::FeatureSlowBTMem, 0ULL }, 98 { "barcelona", "Select the barcelona processor", X86::FeatureSSE3 | X86::FeatureSSE4A | X86::Feature3DNowA | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 99 { "c3", "Select the c3 processor", X86::Feature3DNow, 0ULL }, 100 { "c3-2", "Select the c3-2 processor", X86::FeatureSSE1, 0ULL }, 101 { "core-avx-i", "Select the core-avx-i processor", X86::FeatureSSE42 | X86::FeatureCMPXCHG16B | X86::FeatureAES | X86::FeatureCLMUL | X86::FeatureRDRAND | X86::FeatureF16C, 0ULL }, 102 { "core-avx2", "Select the core-avx2 processor", X86::FeatureSSE42 | X86::FeatureCMPXCHG16B | X86::FeatureAES | X86::FeatureCLMUL | X86::FeatureRDRAND | X86::FeatureF16C | X86::FeatureFMA3 | X86::FeatureMOVBE | X86::FeatureLZCNT | X86::FeatureBMI, 0ULL }, 103 { "core2", "Select the core2 processor", X86::FeatureSSSE3 | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 104 { "corei7", "Select the corei7 processor", X86::FeatureSSE42 | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem | X86::FeatureFastUAMem | X86::FeatureAES, 0ULL }, 105 { "corei7-avx", "Select the corei7-avx processor", X86::FeatureSSE42 | X86::FeatureCMPXCHG16B | X86::FeatureAES | X86::FeatureCLMUL, 0ULL }, 106 { "generic", "Select the generic processor", 0ULL, 0ULL }, 107 { "i386", "Select the i386 processor", 0ULL, 0ULL }, 108 { "i486", "Select the i486 processor", 0ULL, 0ULL }, 109 { "i586", "Select the i586 processor", 0ULL, 0ULL }, 110 { "i686", "Select the i686 processor", 0ULL, 0ULL }, 111 { "istanbul", "Select the istanbul processor", X86::Feature3DNowA | X86::FeatureCMPXCHG16B | X86::FeatureSSE4A | X86::Feature3DNowA, 0ULL }, 112 { "k6", "Select the k6 processor", X86::FeatureMMX, 0ULL }, 113 { "k6-2", "Select the k6-2 processor", X86::Feature3DNow, 0ULL }, 114 { "k6-3", "Select the k6-3 processor", X86::Feature3DNow, 0ULL }, 115 { "k8", "Select the k8 processor", X86::FeatureSSE2 | X86::Feature3DNowA | X86::Feature64Bit | X86::FeatureSlowBTMem, 0ULL }, 116 { "k8-sse3", "Select the k8-sse3 processor", X86::FeatureSSE3 | X86::Feature3DNowA | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 117 { "nehalem", "Select the nehalem processor", X86::FeatureSSE42 | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem | X86::FeatureFastUAMem, 0ULL }, 118 { "nocona", "Select the nocona processor", X86::FeatureSSE3 | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 119 { "opteron", "Select the opteron processor", X86::FeatureSSE2 | X86::Feature3DNowA | X86::Feature64Bit | X86::FeatureSlowBTMem, 0ULL }, 120 { "opteron-sse3", "Select the opteron-sse3 processor", X86::FeatureSSE3 | X86::Feature3DNowA | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 121 { "penryn", "Select the penryn processor", X86::FeatureSSE41 | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem, 0ULL }, 122 { "pentium", "Select the pentium processor", 0ULL, 0ULL }, 123 { "pentium-m", "Select the pentium-m processor", X86::FeatureSSE2 | X86::FeatureSlowBTMem, 0ULL }, 124 { "pentium-mmx", "Select the pentium-mmx processor", X86::FeatureMMX, 0ULL }, 125 { "pentium2", "Select the pentium2 processor", X86::FeatureMMX | X86::FeatureCMOV, 0ULL }, 126 { "pentium3", "Select the pentium3 processor", X86::FeatureSSE1, 0ULL }, 127 { "pentium3m", "Select the pentium3m processor", X86::FeatureSSE1 | X86::FeatureSlowBTMem, 0ULL }, 128 { "pentium4", "Select the pentium4 processor", X86::FeatureSSE2, 0ULL }, 129 { "pentium4m", "Select the pentium4m processor", X86::FeatureSSE2 | X86::FeatureSlowBTMem, 0ULL }, 130 { "pentiumpro", "Select the pentiumpro processor", X86::FeatureCMOV, 0ULL }, 131 { "prescott", "Select the prescott processor", X86::FeatureSSE3 | X86::FeatureSlowBTMem, 0ULL }, 132 { "shanghai", "Select the shanghai processor", X86::Feature3DNowA | X86::FeatureCMPXCHG16B | X86::FeatureSSE4A | X86::Feature3DNowA, 0ULL }, 133 { "westmere", "Select the westmere processor", X86::FeatureSSE42 | X86::FeatureCMPXCHG16B | X86::FeatureSlowBTMem | X86::FeatureFastUAMem | X86::FeatureAES | X86::FeatureCLMUL, 0ULL }, 134 { "winchip-c6", "Select the winchip-c6 processor", X86::FeatureMMX, 0ULL }, 135 { "winchip2", "Select the winchip2 processor", X86::Feature3DNow, 0ULL }, 136 { "x86-64", "Select the x86-64 processor", X86::FeatureSSE2 | X86::Feature64Bit | X86::FeatureSlowBTMem, 0ULL }, 137 { "yonah", "Select the yonah processor", X86::FeatureSSE3 | X86::FeatureSlowBTMem, 0ULL } 138 }; 139 140 141 static inline void InitX86MCSubtargetInfo(MCSubtargetInfo *II, StringRef TT, StringRef CPU, StringRef FS) { 142 II->InitMCSubtargetInfo(TT, CPU, FS, X86FeatureKV, X86SubTypeKV, 0, 0, 0, 0, 29, 50); 143 } 144 145 } // End llvm namespace 146 #endif // GET_SUBTARGETINFO_MC_DESC 147 148 149 #ifdef GET_SUBTARGETINFO_TARGET_DESC 150 #undef GET_SUBTARGETINFO_TARGET_DESC 151 #include "llvm/Support/Debug.h" 152 #include "llvm/Support/raw_ostream.h" 153 // ParseSubtargetFeatures - Parses features string setting specified 154 // subtarget options. 155 void llvm::X86Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) { 156 DEBUG(dbgs() << "\nFeatures:" << FS); 157 DEBUG(dbgs() << "\nCPU:" << CPU); 158 uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS); 159 if ((Bits & X86::Feature3DNow) != 0 && X863DNowLevel < ThreeDNow) X863DNowLevel = ThreeDNow; 160 if ((Bits & X86::Feature3DNowA) != 0 && X863DNowLevel < ThreeDNowA) X863DNowLevel = ThreeDNowA; 161 if ((Bits & X86::Feature64Bit) != 0) HasX86_64 = true; 162 if ((Bits & X86::FeatureAES) != 0) HasAES = true; 163 if ((Bits & X86::FeatureAVX) != 0) HasAVX = true; 164 if ((Bits & X86::FeatureBMI) != 0) HasBMI = true; 165 if ((Bits & X86::FeatureCLMUL) != 0) HasCLMUL = true; 166 if ((Bits & X86::FeatureCMOV) != 0) HasCMov = true; 167 if ((Bits & X86::FeatureCMPXCHG16B) != 0) HasCmpxchg16b = true; 168 if ((Bits & X86::FeatureF16C) != 0) HasF16C = true; 169 if ((Bits & X86::FeatureFMA3) != 0) HasFMA3 = true; 170 if ((Bits & X86::FeatureFMA4) != 0) HasFMA4 = true; 171 if ((Bits & X86::FeatureFastUAMem) != 0) IsUAMemFast = true; 172 if ((Bits & X86::FeatureLZCNT) != 0) HasLZCNT = true; 173 if ((Bits & X86::FeatureMMX) != 0 && X86SSELevel < MMX) X86SSELevel = MMX; 174 if ((Bits & X86::FeatureMOVBE) != 0) HasMOVBE = true; 175 if ((Bits & X86::FeaturePOPCNT) != 0) HasPOPCNT = true; 176 if ((Bits & X86::FeatureRDRAND) != 0) HasRDRAND = true; 177 if ((Bits & X86::FeatureSSE1) != 0 && X86SSELevel < SSE1) X86SSELevel = SSE1; 178 if ((Bits & X86::FeatureSSE2) != 0 && X86SSELevel < SSE2) X86SSELevel = SSE2; 179 if ((Bits & X86::FeatureSSE3) != 0 && X86SSELevel < SSE3) X86SSELevel = SSE3; 180 if ((Bits & X86::FeatureSSE4A) != 0) HasSSE4A = true; 181 if ((Bits & X86::FeatureSSE41) != 0 && X86SSELevel < SSE41) X86SSELevel = SSE41; 182 if ((Bits & X86::FeatureSSE42) != 0 && X86SSELevel < SSE42) X86SSELevel = SSE42; 183 if ((Bits & X86::FeatureSSSE3) != 0 && X86SSELevel < SSSE3) X86SSELevel = SSSE3; 184 if ((Bits & X86::FeatureSlowBTMem) != 0) IsBTMemSlow = true; 185 if ((Bits & X86::FeatureVectorUAMem) != 0) HasVectorUAMem = true; 186 if ((Bits & X86::Mode64Bit) != 0) In64BitMode = true; 187 if ((Bits & X86::ModeNaCl) != 0) InNaClMode = true; 188 } 189 #endif // GET_SUBTARGETINFO_TARGET_DESC 190 191 192 #ifdef GET_SUBTARGETINFO_HEADER 193 #undef GET_SUBTARGETINFO_HEADER 194 namespace llvm { 195 struct X86GenSubtargetInfo : public TargetSubtargetInfo { 196 explicit X86GenSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS); 197 }; 198 } // End llvm namespace 199 #endif // GET_SUBTARGETINFO_HEADER 200 201 202 #ifdef GET_SUBTARGETINFO_CTOR 203 #undef GET_SUBTARGETINFO_CTOR 204 namespace llvm { 205 extern llvm::SubtargetFeatureKV X86FeatureKV[]; 206 extern llvm::SubtargetFeatureKV X86SubTypeKV[]; 207 X86GenSubtargetInfo::X86GenSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) 208 : TargetSubtargetInfo() { 209 InitMCSubtargetInfo(TT, CPU, FS, X86FeatureKV, X86SubTypeKV, 0, 0, 0, 0, 29, 50); 210 } 211 212 } // End llvm namespace 213 #endif // GET_SUBTARGETINFO_CTOR 214 215
